Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.

Abstract: The invention relates to a method and an apparatus for designing a circuit suitable for generating random bits and to a circuit for generating random bits. A random bit string which is used as a binary random number is generated, for example. The proposed method and the apparatus as well as the circuit are used to implement random number generators, for example. A jth specific function from a set of bijective mappings is selected as the jth function, wherein the jth specific function carries out a jth fixed-point-free mapping. At least one ith mapping device is then selected. An ith specific function from a set of bijective mappings is assigned to the ith function, with the result that an ith concatenation of the i functions carries out an ith fixed-point-free mapping.

Abstract: A computer-implemented method includes receiving, with one or more processors, a text-based description of a logic circuit comprising a plurality of logic sub-circuits, determining within the text-based description, with one or more processors, a set of circuit priority indicators for a corresponding set of the logic sub-circuits, and synthesizing, with one or more processors, the logic circuit according to the set of circuit priority indicators to provide a synthesized circuit description. A corresponding computer program product and computer system are also disclosed herein.

Abstract: Systems and methods are provided for calculating a power characteristic of an integrated circuit design. For each standard cell of a gate-level netlist, a path length and a set of attributes are computed. For each leaf-level instance of a register-transfer level (RTL) netlist, a path length and a set of attributes are computed. The standard cells are partitioned into first subsets, each of the first subsets containing standard cells with a same path length and a same set of attributes. For each first subset, a relative percentage for each type of standard cell included in the first subset is calculated. The leaf-level instances are partitioned into second subsets. For each pair of corresponding first and second subsets, standard cells are associated with the leaf-level instances of the second subset based on the relative percentages. A power characteristic of the RTL netlist is calculated based on the associated standard cells.

Abstract: The present disclosure relates to defining and processing hardware description language (HDL) groups. Embodiments may include mapping, using a processor, a set of tool-specific objects into a group graph with one or more groups. Embodiments may also include generating a search order associated with each group. The search order associated with each group may be based upon the hierarchical design configuration of the group graph. Embodiments may further include identifying undefined references from within a first group within the group graph and binding defined references from within the first group to electronic circuit design components. Embodiments may include identifying the undefined references from within a second group within the group graph. The second group may be selected based upon the undefined references and the search order associated with the first group.

Abstract: Designing circuits can include, within a circuit design, detecting, using a processor, a high fan-out net having loads with a same timing requirement, wherein the circuit design is technology specific for a target integrated circuit (IC), determining, using the processor, a region having a predetermined shape and an area sized to fit loads of the high fan-out net within the region on the target IC, and determining, using the processor, a delay of the high fan-out net based upon a distance from a center of the region to an edge of the region. Designing circuits can also include assigning, using the processor, the delay to the high fan-out net.

Abstract: A computer implemented representation of a circuit design is reduced by representing the circuit design as a data structure defining a netlist. A first set of nodes is identified in the netlist that includes datapath nodes, preferably nodes that do not intermingle data and control. The first set of nodes is segmented into segment widths that correspond to uniformly treated segments of the corresponding words. A second set of nodes, including nodes that intermingle data and control, are converted into bit-level nodes. The segmented nodes are analyzed to define reduced safe sizes by applying a computer implemented function. An updated data structure representing the circuit design is then generated using the reduced safe sizes of the segmented nodes.

Abstract: The present disclosure is directed to a method for triple-patterning friendly placement. The method can include creating cell attributes identifying potential risk for triple-patterning design rule checking (TP DRC) violations in both a vertical and a horizontal propagation in a placement region. Based on these cell attributes, placement blockages can be inserted to prevent TP DRC violations after cell placement.

Abstract: Embodiments herein describe a verification process that identifies unate primary inputs in input paths of a property gate. A property gate is logic inserted in a hardware design represented by a netlist which is used to verify the design. Before performing the verification process, a computing system evaluates the netlist to identify the primary inputs in the input paths of the property gate and whether these primary inputs are unate or binate. To do so, in one embodiment, the computing system sets the output of the property gate in an error state and then traverses the input paths of the property gate to identify the values of the logic in the inputs paths that would result in the property gate being in the error state. Based on these polarities, the system can identify the unate and binate primary inputs.

Abstract: A method for data propagation analysis. A data propagation diagram for a circuit design is generated. The data propagation diagram includes a plurality of nodes and a plurality of edges connecting the nodes. The nodes represent data locations in the circuit design and the edges represent data propagation paths between the data locations in the circuit design. A signal trace specifying signal values for the circuit design is analyzed to determine whether data at a first data location of the data locations during a first clock cycle is causally related to the data at a second data location of the data locations during a second clock cycle. A visual animation is displayed on the data propagation diagram indicating movement of the data between a first node of the nodes corresponding to the first data location and a second node of the nodes corresponding to the second data location.

Abstract: The present embodiments relate to regulating the supply voltage of an integrated circuit. The integrated circuit may implement a circuit design. The circuit design implementation may meet timing constraints with timing margins when operated with the integrated circuit at a nominal supply voltage level. The integrated circuit may further include a voltage identification controller. The voltage identification controller may determine a reduced voltage level based at least on the timing margins such that operating the circuit design implementation with the integrated circuit meets timing constraints. The voltage identification controller may direct a voltage regulator, which may be included in the integrated circuit or located outside the integrated circuit, to reduce the supply voltage level from the nominal supply voltage level to the reduced voltage level, thereby reducing the power consumption of the integrated circuit.

Abstract: A method of designing an integrated circuit using a computer implemented circuit design application is disclosed. The method may involve receiving a user-provided value specifying a number of output components to be connected to an input component in the integrated circuit, connecting the input component to each output component of the number of output components in the integrated circuit using computer-implemented fan-out circuit blocks. In addition, generating a circuit design such that one of the fan-out circuit blocks is replaced in the circuit design with connecting components according to a set of parameters.

Abstract: In an embodiment, a device is discussed, the device comprising: a battery, a battery charging circuit configured to allow direct charging of the battery by an external charger, a battery protection circuit configured to protect the battery from damage, coupled to the battery charging circuit; and a connector comprising: at least one sense wire coupled to the battery to sense battery voltage, and at least one wire coupled to the battery via the battery charging circuit and the battery protection circuit, configured to charge the battery.

Abstract: Techniques are described herein for inferring a status of a primary battery for an electronic device in a wireless power delivery environment. In some embodiments, the status of the primary battery can be inferred, without any feedback regarding a status of the primary battery, based on a wireless charging profile of the primary battery and power usage characteristics that are monitored. In some embodiments, the wireless power transmission system utilizes the information inferred about a particular wireless device's primary battery to control or allocate how much wireless power is allocated to a particular wireless power receiver client embedded and/or otherwise associated with the wireless device.

Abstract: A method of making a photomask includes constructing a transmission cross coefficient (TCC) matrix representing an illumination source for supplying light to transmit through the photomask and a pupil for focusing the transmitted light onto a target substrate to produce a set of main features, generating kernels through decomposition of the TCC matrix, selecting ones of the kernels having odd symmetry, generating a field map kernel as a sum of self-convolutions of the odd symmetry kernels, generating a first field map by convolving an area of the photomask corresponding to the set of main features with the field map kernel, and making the photomask corresponding to the first field map. The method may include assigning first sub-resolution assist features (SRAFs) to those portions of the photomask area having corresponding said first field map values exceeding a nonnegative threshold, and making the photomask corresponding to the main features and first SRAFs.

Abstract: There is provided a power storage device including a plurality of modules each including secondary batteries, a charging switch that controls charging to the secondary batteries, a discharging switch that controls discharging of the secondary batteries, and a voltage measuring unit that measures a voltage of the module, and a switch control unit that controls one or both of the charging switch and the discharging switch. The modules are connected in parallel. The switch control unit maintains an on state of the discharging switch for at least one of the modules for a predetermined period, and controls the charging switch of the module in which a maximum module charging current estimated based on the voltage of the module is a predetermined value or less, to be in an on state.

Abstract: The present disclosure relates to customization of a circuit layout using information from a netlist, and more particularly, to customization of a circuit layout using embedded formulas and a netlist. The system includes a CPU, a computer readable memory, and a computer readable storage device. The system also includes first program instructions to generate a graphical layout of a circuit, second program instructions to place a text formula on the graphical layout of the circuit, and third program instructions to activate the text formula in order to customize the graphical layout of the circuit. The first program instructions, the second program instructions, and the third program instructions of the system are stored on the computer readable storage device for execution by the CPU via the computer readable memory.

Abstract: System and method for a portable propane-fueled battery charger. One system includes a battery charger including a propane fuel line and an engine including an output shaft. The engine is configured to receive propane via the propane fuel line and rotationally drive the output shaft. The battery charger further includes an alternator including a rotor and stator coils. The output shaft is mechanically coupled to the rotor, and the rotor is rotationally driven by the output shaft. An electrical current is induced in the stator coils by rotation of the rotor. The battery charger further includes an electrical circuit that receives the electrical current and is configured to determine when a battery pack is coupled to a battery connector, and charge the battery pack.

Abstract: A computer-aided testing is provided for design verification of integrated circuits. More specifically, a method of generating a test case in design rule checking is provided for that includes extracting coordinates of an error marker for a first error identified in an integrated circuit design. The method further includes identifying a first rectangle that encloses the error marker. The method further includes generating a first test case based on data of the integrated circuit design contained within the rectangle. The method further includes determining whether the first test case is representative of the first error. The method further includes in response to determining the first test case is not representative of the first error, identifying a second rectangle that is between the first rectangle and a third rectangle. The method further includes generating a second test case based on data of the integrated circuit design contained within the second rectangle.

Abstract: A bidirectional power converter circuit is controlled via a hysteresis loop such that the bidirectional power converter circuit can compensate for variations and even changes in transmit and receive coil locations without damaging components of the system. Because the bidirectional power converter is capable of both transmitting and receiving power (at different times), one circuit and board may be used as the main component in multiple wireless power converter designs. A first bidirectional power converter is employed in a sealed battery unit having no external electrical contacts. A second bidirectional power converter is employed in a corresponding cart bidirectional power converter assembly. The battery unit and the cart bidirectional power converter assembly cooperate to wirelessly transmit power from the battery unit to a load of the cart bidirectional power converter assembly and from a power source to the battery unit via the cart bidirectional power converter assembly.