Abstract: A method for producing a solid-state imaging device including a photodetector including implanting two different dopant impurity ions, each producing the second conductivity type and having different diffusion coefficients in a first conductivity type semiconductor layer; thermally diffusing the implanted ions to produce a second conductivity type region including a relatively deep second conductivity type subregion and a relatively shallow second conductivity type region having a higher dopant impurity concentration than said relatively deep second conductivity type subregion; forming a charge transfer electrode on said semiconductor layer such that an edge of said electrode lies adjacent part of the junction between said semiconductor layer and said second conductivity type region; and implanting a dopant impurity producing the first conductivity type in said second relatively shallow second conductivity type subregion using said charge transfer electrode as a mask to produce a first conductivity type impur
Abstract: A method for exposing a surface of an object to a radiation beam for writing a pattern thereon. The method includes the steps of producing a radiation, shaping the radiation to form a shaped radiation beam such that the shaped radiation beam has an elongated cross section extending in a first direction, directing the shaped radiation beam to a reticle that carries a transparent pattern and an opaque pattern for patterning the shaped radiation beam to form a patterned beam in accordance with the transparent and opaque patterns upon passage through the reticle and for illuminating the surface of the object by the patterned beam, and maintaining a focusing of the patterned beam on the surface of the object by moving said object, wherein the step of directing the patterned beam includes a step for scanning the patterned beam in a second, different direction over a surface of the reticle.
Abstract: A method of manufacturing a semiconductor film and a semiconductor device is disclosed. The method comprises the steps of:forming a non-single crystal semiconductor film on a surface by sputtering in an atmosphere comprising hydrogen; andcrystallizing the non-single crystal semiconductor film at a temperature of 450.degree. C. to 750.degree. C.
Type:
Grant
Filed:
September 18, 1991
Date of Patent:
August 17, 1993
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
Abstract: A method for interconnecting layers in a semiconductor device is disclosed. The device includes a lower conductive layer formed by capping a second conductive layer on a first conductive layer, a contact window formed in an inter-insulating layer on the lower conductive layer, and an upper conductive layer connected to the lower conductive layer through the contact window. The contact window is formed by removing a portion of the inter-insulating layer where the contact will be formed using a first etching gas, and removing a portion of the second conductive layer where the contact will be formed using a second etching gas. The contact resistance becomes uniform by preventing the formation of a non-volatile mixture in the contact window, and the reliability of the device is improved by planarizing the surface of the lower conductive layer.
Abstract: A method for the making of an optoelectronic device comprising at least one quantum well, the barriers of which are made of GaInP and the well of which is made of GaAs, is carried out by the interdiffusion of elements between barriers and quantum wells in such a way that there is a migration of at least indium elements from a barrier to the quantum well. The method can be applied to the making of quantum well lasers, photodetectors and optical guides.
Abstract: A method of providing electrical contact between a gate of a transistor device and an active area remote of the transistor device includes: a) providing a first layer of a conductivity capable material over a gate insulative layer; b) etching the first and gate layers to expose a contact area; c) providing a second layer of a second material over the contact area and first layer; d) etching the second layer selectively relative to the first material and the substrate to provide a pair of buried contact spacers over respective opposing edges of the first layer in the contact area, and to reexpose a portion of the contact area and the first layer; e) providing a third layer of a conductivity capable material over the first layer, the buried contact spacers and the exposed portion of the contact area; f) etching the first and third layers to define a transistor gate of one device and a transistor gate of another device, and to interconnect the transistor gate of the another device to the portion of the contact a
Abstract: A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layer disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.
Abstract: This is a method of forming a vertical transistor device. The method comprises: forming a n-type source layer 12; forming a p+ carbon doped gate layer 14; forming a gate structure from the gate layer; and forming a n-type drain layer 16 over the gate structure to provide a buried carbon doped gate structure. The buried carbon doped gate structure provides a very small device with favorable on-resistance, junction capacitance, gate resistance, and gate driving voltage. Other devices and methods are also disclosed.
Type:
Grant
Filed:
April 30, 1992
Date of Patent:
July 27, 1993
Assignee:
Texas Instruments Incorporated
Inventors:
Han-Tzong Yuan, Tae S. Kim, Francis J. Morris
Abstract: A method for manufacturing a semiconductor device which includes a step of evaluating the dopant profile, in at least the depth dimension, in a processed or partially processed wafer. The evaluation is performed nondestructively, by measuring a differential reflectivity spectrum of the doped portion of the wafer. The resulting spectrum can be related to the Fourier transform of the dopant profile in the depth dimension.
Type:
Grant
Filed:
May 4, 1992
Date of Patent:
July 20, 1993
Assignee:
AT&T Bell Laboratories
Inventors:
Tao-Yuan Chang, Rubens da S. Miranda, Harry W. K. Tom
Abstract: A method for manufacturing a memory integrating a ferroelectric film, having properties such as excellent information rewriting times, breakdown voltage and leak current and the like, by forming a lower electrode sandwiching a ferroelectric material on a high concentration diffusion layer, such as source and drain regions, formed on a semiconductor substrate, and forming a polysilicon film between the electrode and the high concentration diffusion layer. A semiconductor device formed by the method of the present invention is also disclosed.
Abstract: A method of diffusing mercury into a crystalline compound semiconductor film including mercury includes forming an amalgam on a region of the semiconductor film into which mercury is to be diffused, forminq a protective film on the amalgam, and annealing, whereby mercury from the amalgam diffuses into the semiconductor film and the protective film prevents the mercury from escaping. Therefore, a complicated temperature profile is not required and the mercury diffusion is carried out without sealing the semiconductor film in a quartz tube. As a result, the instruments and materials used in the diffusion process are easily handled and the diffusion of mercury into a large-sized semiconductor film is possible.
Abstract: Epitaxial layers of II-VI semiconductors in-situ doped with high concentrations of a stable acceptor-type impurity and capped with a diffusion-limiting layer, when subjected to a rapid thermal anneal at a temperature between 700 and 950 degrees C., exhibit a high conversion of the impurities to acceptors, sufficient to render the layers p-type.
Abstract: An electrically erasable programmable read only memory (EEPROM) cell is fabricated by forming first and second first field oxide (FOX1) regions in a P-well in an N-substrate to define a P-type active device region. First and second buried N+ bit lines are formed in the P-well adjacent to the FOX1 regions; bit lines define a P-type channel region therebetween. First and second second field oxide (FOX2) regions are formed adjacent to the FOX1 regions and overlying the buried N+ bit-lines. A layer of gate oxide 300-500.ANG. thick is formed on the P-well between the FOX2 regions. A layer of polysilicon is formed over the gate oxide to extend over only a first portion of the P-type channel region. A tunnel window is defined on the gate oxide over the P-type channel region and overlapping the floating gate edge. The gate oxide is removed from the tunnel window and tunnel oxide about 80-100.ANG. thick is formed.
Abstract: A method of diffusing a P type impurity into a semiconductor substrate includes selectively implanting ions of a first P type impurity into a semiconductor substrate and thermally diffusing a second P type impurity into the semiconductor substrate at least in a region where the first P type impurity ions are implanted. The diffusion speed of the P type impurity is increased in the ion implantation region whereby a P type impurity diffusion region which nearly corresponds in extent to the ion implantation region is obtained. The P type diffusion region can be precisely produced with a high dopant impurity concentration.
Abstract: The invention relates to such semiconductor devices comprising: a wiring layer with a predetermined pattern formed over a major surface of a semiconductor substrate through an insulating film, a diffusion layer formed under a contact hole formed in said insulating film in an adjacent region of the wiring layer, and a conductive layer deposited into said contact hole in a state of being connected to said wiring layer.
Abstract: A manufacturing method of a semiconductor memory device includes the steps of selectively forming a field oxide film and a gate oxide film on a semiconductor substrate, depositing a first conductive layer on an entire surface of the resultant structure, selectively etching the first conductive layer located in a region other than an element region, depositing a second conductive layer on an entire surface of the resultant structure, and etching the first conductive layer and the second conductive layer using the same mask to form a plurality of floating gates by the first conductive layer and to form a plurality of control gates by the second conductive layer, wherein the step of selectively etching the first conductive layer includes the first etching step of forming cell slits for separating the plurality of floating gates from each other and the second etching step of forming removed regions each of which includes only one end of each of the plurality of control gates.
Abstract: A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application specific integrated circuit formed of such master slice is defined. In the IC, transistor gate cells, which are the same type of cells used for other purposes in the IC, are configured to serve the input and output function. Accordingly, the input and output function may be placed on any location in the IC. As an incident to personalization of the wafer saw lanes are formed of channels that extend over transistor cells and the latter cells are consequently destroyed in slicing the wafer. Means are also disclosed for an improved E-beam lithographic apparatus which permits an IC chip to be placed on an area of a wafer that is occupied by a marker, providing a wiring or macro design that avoids the marker.
Type:
Grant
Filed:
February 4, 1991
Date of Patent:
June 8, 1993
Assignee:
TRW Inc.
Inventors:
James M. Anderson, Andrew R. Coulson, Vincent J. Demaioribus, Henry T. Nicholas
Abstract: First, a low-concentration impurity layer is formed by obliquely implanting an n-type impurity at a prescribed angle with respect to the surface of a p-type semiconductor substrate, using a gate electrode formed on the semiconductor substrate as a mask. Thereafter a sidewall spacer is formed on the sidewall of the gate electrode, and then a medium-concentration impurity layer is formed by obliquely implanting an n-type impurity to the surface of the semiconductor substrate. Thereafter a high-concentration impurity layer is formed by substantially perpendicularly implanting an n-type impurity with respect to the surface of the semiconductor substrate. According to this method, the low-concentration impurity layer in source and drain regions having triple diffusion structures can be accurately overlapped with the gate electrode, with no requirement for heat treatment for thermal diffusion.
Abstract: An improved process is provided for fabricating short channel complementary metal oxide semiconductor devices. The devices comprise source and drain regions separated by gate regions. The process comprises forming a shallow channel doping region (12') beneath the surface of a semiconductor (10) and forming source-drain regions (20') of opposite conductivity type (formerly known as lightly doped drain structures) on either side of the shallow doping region. A gate oxide (16) is formed on the surface of the semiconductor above the shallow channel doping region and a gate electrode (18) is formed to the gate oxide subsequent to the formation of the shallow channel doping region. The process permits spacing of the channel doping from the source-drain doping with self-alignment. Further, the doping of the source-drain regions is not constrained to the values of the lightly-doped structures of the prior art.
Type:
Grant
Filed:
May 7, 1992
Date of Patent:
June 1, 1993
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Darrell M. Erb, Rajat Rakkhit, Farrokh Omid-Zohoor
Abstract: A semiconductor over insulator transistor is provided preferably of a lightly doped drain ("LDD") profile. LDD transistor (74) includes a semiconductor mesa (76) formed over an insulating layer (94) which overlies a semiconductor substrate (96). Semiconductor mesa (76) includes a source region (78) and a drain region (80) at opposite ends thereof. A body node (82) is disposed between source and drain regions (78,80). A low resistance contact region (98) lies along substantially the entire width of body region (82) and contacts a vertical contact which permits electrical contact from the top surface of semiconductor mesa (76) to low resistance contact region (98). Low resistance contact region (98) may be extended to fully underlie source region (78) such that the vertical contact may be moved away from body node (82).