Patents Examined by C. Ngo
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Patent number: 5303178Abstract: A multiplying system based on the Booth's algorithm, comprises a Booth's decoder having a first input receiving a multiplier "Y" and a second input receiving a mode signal designating either a first multiplication of "X.times.Y" (where "X" is a multiplicand) or a second multiplication of "-X.times.Y". The Booth's decoder generates a Booth's decoded value and a sign selection signal to a partial product generation circuit which also receives the multiplicand "X", so that the partial product generation circuit generates either a first partial product of "X.times.Y" or a second partial product of "-X.times.Y" in accordance with the sign selection signal. An output of the partial product generation circuit is summed by a partial product summing circuit, and an output of the partial product summing circuit is added to a value "A" stored in an output register by an arithmetic unit. Thus, the accumulating multiplication "A=A.+-.X.times.Type: GrantFiled: January 31, 1992Date of Patent: April 12, 1994Assignee: NEC CorporationInventor: Yasushi Ozaki
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Patent number: 5285405Abstract: An inner product calculating circuit for executing a calculation of an inner product on the basis of one or more vector data and one or more coefficients. The circuit comprises a selective inverter for selectively inverting individual bits of the vector data; a bit position shifter for shifting, in accordance with the coefficients, the bit positions of the vector data inverted selectively by the selective inverter; a bit supplementer for supplementing, with either "1" or "0", any vacant bit of the vector data where the bit positions have been shifted by the bit position shifter; and an accumulator for accumulating the initial values preset in conformity with the coefficients and the vector data supplemented with "1" or "0" in any vacant bit thereof by the bit supplementer.Type: GrantFiled: September 9, 1992Date of Patent: February 8, 1994Assignee: Sony CorporationInventor: Mitsuharu Ohki
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Patent number: 5266918Abstract: A serial comparator for comparing serially input data values with an internal data value in order to determine a command implementation requirement, having NOR gates for logic-adding two input data under the control of an output value obtained through an exclusive NOR gate, an inverter and a NAND gate, two latching circuits for latching the output from the NOR gate, two inverters for inverting the outputs from the latching circuits, and a NOR gate for outputting the equivalent value out of the inverted outputs from the two inverters, to output the lowermost bit value as a feedback to the NAND gate so as to output the uppermost address bit value. Accordingly, even in the case where the bit numbers of the input data and the internal data are variable, the operating characteristic becomes adapted to the semiconductor in which the input or output is carried out serially.Type: GrantFiled: October 21, 1991Date of Patent: November 30, 1993Assignee: Samsung Electronics, Co., Ltd.Inventors: Dae S. Won, Jun S. Hwangbo, Jae Y. Do
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Patent number: 5251166Abstract: This redundant binary type digital operation unit is provided with a redundant binary adder which gives a plurality of carry margin digits to the word length of the input redundant binary data on the higher digit side and further gives a protection digit for overflow judgment at the highest position to form the entire operation word length. It is also provided with a fixed value data output circuit to which a carry signal from the redundant binary adder showing whether a carry exists or not is input and which outputs the maximum value data when the carry signal value is "1" and the minimum value data when the carry signal value is a value other then "1", as well as a selection circuit which selects and outputs the output data from the redundant binary adder when the sign bit of the protection digit at the highest position sent from the redundant binary adder is "0", and the maximum or minimum value data from the fixed value data output circuit when the sign bit is "1".Type: GrantFiled: April 7, 1992Date of Patent: October 5, 1993Assignee: NEC CorporationInventor: Ryuji Ishida
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Patent number: 5189634Abstract: A digital signal processing apparatus is disclosed. The apparatus is particularly suited for detecting a digital signal containing a frequency component in a noisy environment. It uses a distributed arithmetic concept for hardware realization. The use of specific coefficients and hardware arrangement has resulted in a reduction of memory location requirement. The invention finds the main application in the area of telephony in which detection of a variety of signal tones is required for various operations of telephone functions.Type: GrantFiled: March 28, 1991Date of Patent: February 23, 1993Assignee: Northern Telecom LimitedInventors: Gernot Eberle, Guy J. Chaput