Abstract: An efficient cache write technique useful in digital computer systems wherein it is desired to achieve single cycle cache write access even when the processor cycle time does not allow sufficient time for the cache control to check the cache "tag" for validity and to reflect those results to the processor within the same processor cycle. The novel method and apparatus comprising a two-stage cache access pipeline which embellishes a simple "write-thru with write-allocate" cache write policy.

Abstract: An interface system for a copying system, wherein a frame of transmission data employing a serial communication between a copying machine main body and peripheral devices thereof comprises an address block, a data block and a checksum data block, an optional device corresponding to an address transmitted from the main body transfers data to the main body when the data received coincides with checksum data obtained in the device based on the received data and the transfer of the data is complete when the main body confirms that the transmission address coincides with the transferred data, and when the transferred data is not returned from the optional device or the coincidence is not confirmed, it is determined that a transmission error occurs and data is transmitted from the main body again, whereby reliability of transmission is improved.

Abstract: In a data processing system using a virtual memory adressing scheme, certain software instructions call for the virtual address to be stored in a base register. The virtual address stored in the base register is incremented or decremented during the read out cycle of the previous operand to address the next operand. If the operand is not in physical memory, then the contents of the base register is restored to its original value.

Abstract: The subject apparatus includes a number of data bases which are used by the expert system software to manage the computer system data storage devices. One element provided in this apparatus is a set of data storage device configuration data that provides a description of the various data storage devices and their interconnection in the computer system. A second element is a knowledge data base that includes a set of functional rules that describe the data storage device management function. These rules indicate the operational characteristics of the various data storage devices and the steps that need to be taken to provide the various improvement functions required of the computer system memory.

Abstract: A finite-state machine (30), which receives its input on INPUT lines (32) and generates its output on OUTPUT lines (34), is implemented with a content-addressable memory (46), whose output is the address of the location containing the data word presented to the content-addressable memory as its input. The content-addressable memory's input data word is the concatenation of the finite-state-machine input and the content-addressable-memory output, while the content-addressable-memory output is the output of the finite-state machine.