Abstract: A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, and a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: An optical sensing device can include: a semiconductor having a photosensitive region; an optical structure located above the photosensitive region; and where the optical structure comprises alternately stacked light-filtering layers and light-transmitting layers, in order to block large-angle incident light from entering the photosensitive region.

Abstract: According to one embodiment, a ceramic metal circuit board is a ceramic metal circuit board formed by bonding metal circuit plates to at least one surface of a ceramic substrate. At least one of the metal circuit plates has an area of not less than 100 mm2 and includes a concave portion having a depth of not less than 0.02 mm within a range of 1% to 70% of a surface of the at least one of the metal circuit plates. The concave portion is provided not less than 3 mm inside from an end of the metal circuit plate.

Abstract: A light-emitting device includes a substrate including a top surface; a semiconductor stack including a first semiconductor layer, an active layer and a second semiconductor layer formed on the substrate, wherein a portion of the top surface is exposed; a distributed Bragg reflector (DBR) formed on the semiconductor stack and contacting the portion of the top surface of the substrate; a metal layer formed on the distributed Bragg reflector (DBR), contacting the portion of the top surface of the substrate and being insulated with the semiconductor stack; and an insulation layer formed on the metal layer and contacting the portion of the top surface of the substrate.

Abstract: A photo sensor circuit includes: a photo transistor; a first switching transistor; a second switching transistor; and a capacitance element. The photo transistor includes: a gate connected to a first wiring; a source connected to a second wiring; and a drain. The first switching transistor includes: a gate connected to a third wiring; a source connected to a fourth wiring; and a drain connected to the drain of the photo transistor. The capacitance element includes: a first terminal connected to the drain of the photo transistor; and a second terminal connected to the source of the first switching transistor. The second switching transistor includes: a gate connected to a gate line; a source connected to a signal line; and a drain connected to the first terminal of the capacitance element. The photo transistor, first switching transistor, and second transistor each include an oxide semiconductor layer as a channel layer.

Abstract: A voltage tunable solar-blind UV detector using a EG/SiC heterojunction based Schottky emitter bipolar phototransistor with EG grown on p-SiC epi-layer using a chemically accelerated selective etching process of Si using TFS precursor.

Abstract: A package includes an interposer structure including a first via; a first interconnect device including conductive routing and which is free of active devices; an encapsulant surrounding the first via and the first interconnect device; and a first interconnect structure over the encapsulant and connected to the first via and the first interconnect device; a first semiconductor die bonded to the first interconnect structure and electrically connected to the first interconnect device; and a first photonic package bonded to the first interconnect structure and electrically connected to the first semiconductor die through the first interconnect device, wherein the first photonic package includes a photonic routing structure including a waveguide on a substrate; a second interconnect structure over the photonic routing structure, the second interconnect structure including conductive features and dielectric layers; and an electronic die bonded to and electrically connected to the second interconnect structure.

Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

Abstract: A disclosed transistor structure includes a gate electrode, an active layer, a source electrode, a drain electrode, an insulating layer separating the gate electrode from the active layer, and a carrier modification device that reduces short channel effects by reducing carrier concentration variations in the active layer. The carrier modification device may include a capping layer in contact with the active layer that acts to increase a carrier concentration in the active layer. Alternatively, the carrier modification device may include a first injection layer in contact with the source electrode and the active layer separating the source electrode from the active layer, and a second injection layer in contact with the drain electrode and the active layer separating the drain electrode from the active layer. The first and second injection layers may act to reduce a carrier concentration within the active layer near the source electrode and the drain electrode.

Abstract: An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.

Abstract: An optical modulator includes an emitter layer with N-type doping having a first bandgap energy; a base layer with P-type doping having a second bandgap energy; a sub-emitter layer disposed between the emitter layer and the base layer, wherein the sub-emitter layer has a third bandgap energy that is less than both the first bandgap energy and the second bandgap energy. The sub-emitter layer provides a barrier to electrons flowing from the emitter layer, while allowing photo-generated holes to recombine in the sub-emitter layer thereby mitigating current amplification.

Abstract: A display device includes a first display area including a plurality of first pixel electrodes, and a second display area including a plurality of second pixel electrodes. A first pitch in a first direction of the plurality of first pixel electrodes is smaller than a second pitch in the first direction of the plurality of second pixel electrodes, and a length in the first direction of the first pixel electrodes is smaller than a length in the first direction of the second pixel electrode.

Abstract: A method, apparatus and system with an autonomic, self-healing polymer capable of slowing crack propagation within the polymer and slowing delamination at a material interface.

Abstract: A semiconductor light-receiving element, includes: a semiconductor substrate; a high-concentration layer of a first conductivity type formed on the semiconductor substrate; a low-concentration layer of the first conductivity type formed on the high-concentration layer of the first conductivity type and in contact with the high-concentration layer of the first conductivity type; a low-concentration layer of a second conductivity type configured to form a PN junction interface together with the low-concentration layer of the first conductivity type; and a high-concentration layer of the second conductivity type formed on the low-concentration layer of the second conductivity type and in contact with the low-concentration layer of the second conductivity type. The low-concentration layers have a carrier concentration of less than 1×1016/cm3. The high-concentration layers have a carrier concentration of 1×1017/cm3 or more.

Abstract: A display device includes a first display area including a plurality of first pixel electrodes, and a second display area including a plurality of second pixel electrodes. A first pitch in a first direction of the plurality of first pixel electrodes is smaller than a second pitch in the first direction of the plurality of second pixel electrodes, and a length in the first direction of the first pixel electrodes is smaller than a length in the first direction of the second pixel electrode.

Abstract: Germanium (Ge)-Silicon (Si) structures, optoelectronic devices and method for forming same. A structure comprises a Si substrate, a Ge seed layer and a Ge epitaxial layer separated by respective interfaces that share a common plane normal, wherein the Si substrate and the Ge seed layer have a same first doping type with a first doping level, and a locally doped region formed in the Si layer adjacent to the Ge seed layer and having a second doping type with a second doping level, wherein the locally doped region is designed to reduce leakage currents between the Si substrate and the Ge epitaxial layer when an electrical bias is applied to the structure.

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.

Abstract: Transistor structures employing metal chalcogenide channel materials may be formed where a chalcogen is introduced into at least a portion of a precursor material that comprises reactive metal(s). The precursor material may be substantially metallic, or may be a metallic oxide (e.g., an oxide semiconductor). The metal(s) may be transition, Group II, Group III, Group V elements, or alloys thereof. An oxide of one or more such metals (e.g., IGZO) may be converted into a chalcogenide (e.g., IGZSx or IGZSex) having semiconducting properties. The chalcogenide formed in this manner may be only a few monolayers in thickness (and may be more thermally stable than many oxide semiconductors. Where not all of the precursor material is converted, a transistor structure may retain the precursor material, for example as part of a transistor channel or a gate dielectric. Backend transistors including metal chalcogenide channel materials may be fabricated over silicon CMOS circuitry.

Abstract: Contact over active gate (COAG) structures with conductive gate taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. Each of the plurality of gate structures includes a conductive tap structure protruding through the corresponding gate insulating layer. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. An opening is in the interlayer dielectric material and exposes the conductive tap structure of one of the plurality of gate structures. A conductive structure is in the opening and is in direct contact with the conductive tap structure of one of the plurality of gate structures.

Abstract: Devices, methods and techniques are disclosed to suppress electrical discharge and breakdown in insulating or encapsulation material(s) applied to solid-state devices. In one example aspect, a multi-layer encapsulation film includes a first layer of a first dielectric material and a second layer of a second dielectric material. An interface between the first layer and the second layer is configured to include molecular bonds to prevent charge carriers from crossing between the first layer and the second layer. The multi-layer encapsulation configuration is structured to allow an electrical contact and a substrate of the solid-state device to be at least partially surrounded by the multi-layer encapsulation configuration.