Abstract: A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

Abstract: To provide a nitride semiconductor light-emitting element in which a buffer layer provided between an n-type nitride semiconductor layer and a p-type nitride semiconductor layer has a first buffer layer expressed by an equation of Inx1Ga1-x1N (0<x1?1) and a second buffer layer expressed by an equation of Inx2Ga1-x2N (0?x2<1, x2<x1) alternately laminated, an In composition x1 of the first buffer layer is changed, and the In composition x1 of at least one layer of the first buffer layers is higher than an In composition of the active layer, and a method for producing the same.

Abstract: A semiconductor light emitting device and package containing the same include: a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. A light extraction layer is disposed on the light emitting structure and includes a light-transmissive thin film layer having light transmittance, a nano-rod layer including nano-rods disposed on the light-transmissive thin film layer, and a nano-wire layer including nano-wires disposed on the nano-rod layer.

Abstract: The invention relates to a method for manufacturing, by means of epitaxy, a monocrystalline layer of GaN on a substrate, wherein the coefficient of thermal expansion is less than the coefficient of thermal expansion of GaN, comprising the following steps: (b) three-dimensional epitaxial growth of a layer of GaN relaxed at the epitaxial temperature, (c1) growth of an intermediate layer of BwAlxGayInzN, (c2) growth of a layer of BwAlxGayInzN, (c3) growth of an intermediate layer of BwAlxGayInzN, at least one of the layers formed in steps (c1) to (c3) being an at least ternary III-N alloy comprising aluminium and gallium, (d) growth of said layer of GaN.

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

Abstract: A method of three dimensional heterogeneous integration including forming HBT devices on a first substrate, each HBT device having a collector, removing the first substrate, forming first bonding pads on each collector of the heterojunction bipolar transistor devices, forming high electron mobility transistor (HEMT) devices on a first side of a growth substrate, wherein the growth substrate comprises a thermally conductive substrate, such as SiC or diamond, forming second bonding pads on the first side of the growth substrate, aligning and bonding the first bonding pads to the second bonding pads, forming CMOS devices on a Si substrate, bonding the CMOS devices on the Si substrate to a second side of the growth substrate, and forming selectively interconnects between the HBT devices, the HEMT devices, and the CMOS devices by forming vias and first and second level metal interconnects.

Abstract: A display panel including a first switching element, a first pixel electrode electrically connected to the first switching element, the first pixel electrode including a reflective material. A first light emitting layer is disposed on the first pixel electrode, and emits light having a first color when a voltage is applied to the first pixel electrode. A thin encapsulation film is disposed on the first light emitting layer, and protects the first light emitting layer. A pressure sensitive adhesive layer is disposed on the thin encapsulation film, and a first color filter is disposed on the pressure sensitive adhesive layer, corresponding to the first light emitting layer, and has the first color.

Abstract: Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. In one or more embodiments, certain regions of the cell structure may be sensitive to damage. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. Furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material.

Abstract: An isolation region is provided. The isolation region includes a first groove and an insulation layer filling the first groove. The first groove is embedded into a semiconductor substrate and includes a first sidewall, a bottom surface and a second sidewall that extends from the bottom surface and joins to the first sidewall. An angle between the first sidewall and a normal line of the semiconductor substrate is larger than a standard value. A method for forming an isolation region is further provided. The method includes: forming a first trench on a semiconductor substrate, wherein an angle between a sidewall of the first trench and a normal line of the semiconductor substrate is larger than a standard value; forming a mask on the sidewall to form a second trench on the semiconductor substrate by using the mask; and forming an insulation layer to fill the first and second trenches. A semiconductor device and a method for forming the same are still further provided.

Abstract: A rectangular capacitor for dynamic random access memory (DRAM) and a dual-pass lithography method to form the same are described. For example, a capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A cup-shaped metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the cup-shaped metal plate. A trench-fill metal plate is disposed on the second dielectric layer. The second dielectric layer isolates the trench-fill metal plate from the cup-shaped metal plate. The capacitor has a rectangular or near-rectangular shape from a top-down perspective.

Abstract: A field effect transistor includes a substrate, a first graphene (Gr) layer on the substrate, a second graphene (Gr) layer on the substrate, a fluorographene (GrF) layer on the substrate and between the first and second graphene layers, a first ohmic contact on the first graphene layer, a second ohmic contact on the second graphene layer, a gate aligned over the fluorographene layer, and a gate dielectric between the gate and the fluorographene layer and between the gate and the first and second ohmic contacts.

Abstract: A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.

Abstract: Disclosed herein an image sensor chip, including a substrate having at least one via extending through at least one inter layer dielectric (ILD); a first conductive layer over the ILD, wherein the first conductive layer has a first thickness; a second conductive layer over the first conductive layer, wherein the second conductive layer has a second thickness of less than the first thickness; a polymer layer over the second conductive layer, the polymer layer including a cavity; a plurality of cavity components in the cavity; and protective layer contacting the polymer layer and covering the cavity.

Abstract: An organic light emitting display device is disclosed which includes: a substrate defined into a display area and a non-display area; a light emission diode layer formed on the substrate and configured to emit light; a TFE layer formed on the light emission diode layer and configured to protect the light emission diode layer; an intrusive moisture guide layer configured to prevent moisture intrusion into the light emission diode layer; and a getter configured to absorb moisture which is guided by the intrusive moisture guide layer.

Abstract: A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffener. The patterned adhesive layer is confined to kerf regions, which are subsequently removed during singulation. Each hole in the patterned adhesive layer has an area that is greater than the area of a bottomside interconnect footprint of the coreless substrate. The patterned adhesive layer may include a permanent adhesive that is thermally curable or ultraviolet-curable. The composition of the stiffener can be tailored so that the thermal coefficient of expansion of the stiffener provides tensile stress to the coreless substrate layer at room temperature and at the bonding temperature. The tensile stress applied to the coreless substrate layer prevents or reduces warpage of the coreless substrate layer during bonding. Upon dicing, bonded stacks of a semiconductor chip and a coreless substrate can be provided without adhesive thereupon.

Abstract: The present invention provides a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material; and a film for flip chip type semiconductor back surface provided on the pressure-sensitive adhesive layer, in which the film for flip chip type semiconductor back surface contains a black pigment.

Abstract: A method for fabricating the device includes patterning a first structure and a second structure on a semiconductor device. A first angled ion implantation is applied to the second structure such that the first structure is protected and a second angled ion implantation is applied to the first structure such that the second structure is protected, wherein exposed portions of the first and second structures have an altered rate of oxidation. Oxidation is performed to form thicker or thinner oxide portions on the exposed portions of the first and second structures relative to unexposed portions of the first and second structures. Oxide portions are removed to an underlying layer of the first and second structures. The first and second structures are removed. Spacers are formed about a periphery of remaining oxide portions. The remaining oxide portions are removed. A layer below the spacers is patterned to form integrated circuit features.

Abstract: A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

Abstract: A semiconductor device having a dummy active region for metal ion gathering, which is capable of preventing device failure due to metal ion contamination, and a method of fabricating the same are provided. The semiconductor device includes active regions defined by an isolation layer in a semiconductor substrate and ion-implanted with an impurity, and a dummy active region ion-implanted with an impurity having a concentration higher than that of the impurity in the active region and configured to gather metal ions.

Abstract: A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.