Abstract: A moving window history of at least one previous data address accessed by a processor is maintained, the at least one previous data address in the history each being associated with an index. A difference between a current data address and one of the at least one previous data address in the history is determined. The difference and the index associated with the one of the at least one previous data address in the history are provided as a representation of the current address.

Abstract: A method and system for performing logical to physical address translations in a memory is disclosed, wherein the memory includes a translation cache containing a subset of a plurality of entries mapping logical block addresses to physical locations of the memory. Aspects of the exemplary embodiment include receiving from a processor a read/write request for a logical block and context information regarding the logical block, the context information including at least one of a relationship of the logical block to other logical blocks and a description of future activity associated with the logical block; and pre-fetching a first entry into the translation cache based on the context information so that the first entry required to satisfy a future request is available in the translation cache when the future request is received.

Abstract: A memory apparatus having a cache memory including cache segments, and memorizing validity data indicative of whether or not each of the sectors contained in each cache segment is a valid sector inclusive of valid data; and a cache controlling component for controlling access to the cache memory. The cache controlling component includes a detecting component for detecting, when writing a cache segment back to the main memory, areas having consecutive invalid sectors by accessing validity data corresponding to the cache segment, and a write-back controlling component issuing a read command to the main memory, the read command being for reading data into each area detected, making the area a valid sector, and writing the data in the cache segment back to the main memory.

Abstract: A storage system comprises a plurality of control modules having a plurality of cache memories respectively. One or more dirty data elements out of a plurality of dirty data elements stored in a first cache memory in a first control module are copied to a second cache memory in a second control module. The one or more dirty data elements stored in the second cache memory are backed up to a non-volatile storage resource. The dirty data elements backed up from the first cache memory to the non-volatile storage resource are dirty data elements other than the one or more dirty data elements of which copying has completed, out of the plurality of dirty data elements.

Abstract: A method and apparatus associated with transferring data from a remote device to a recipient device having a first memory space and a second memory space. The method includes issuing a transfer command from the remote device to request transferring a set of data to the second memory space; temporarily storing the set of data in the first memory space pending a transfer to the second memory space; and appending the set of data to other sequential data in the first memory to obtain a transfer data block of a predetermined size for transfer to the second memory space. A corresponding apparatus is provided comprising circuitry configured to buffer write commands by characterizing each write command as being either a sequential write or a random write, and responsively appending data associated with sequential write commands in order to obtain a transfer block of a predetermined size.

Abstract: A flash memory storage system and a data writing method thereof are provided. The flash memory storage system includes a controller, a connector, a cache memory, a SLC NAND flash memory and a MLC NAND flash memory. When the controller receives data to be written into the MLC NAND flash memory from a host system, the data is temporarily stored in the cache memory first and then is written into the MLC NAND flash memory from the cache memory. And, the controller may backup the data stored in the cache memory to the SLC NAND flash memory. Accordingly, it is possible to reduce a response time for a flush command, thereby improving a performance of the flash memory storage system.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design can be provided. The design structure includes a symmetric multiprocessing (SMP) system. The system includes a plurality of nodes. Each of the nodes includes a node controller and a plurality of processors cross-coupled to one another. The system also includes at least one cache directory coupled to each node controller, and, invalid state transition logic coupled to each node controller. The invalid state transition logic includes program code enabled to identify an invalid state transition for a cache line in a local node, to evict a corresponding cache directory entry for the cache line, and to forward an invalid state transition notification to a node controller for a home node for the cache line in order for the home node to evict a corresponding cache directory entry for the cache line.

Abstract: A method and a computer readable medium having executable instructions are provided. The method and instructions when executed generates a first look-up key from a group of look-up key units stored in a data storage, generation of the first look up key being completed prior to the completion of a key generation processing cycle. A next look-up key unit from the group of look-up key units stored in the data storage may be skipped over when the next look up key corresponds to a second look-up key that has a key length equal to or smaller than a predetermined key length. A third look-up key unit may be selected from the group of look-up key units, the third look-up key unit associated with a third look-up key having a key length greater than a second predetermined key length, the second predetermined key length being greater than the first predetermined key length. The first look-up key and a portion of the third look-up key sequentially may be output during the same output processing cycle.

Abstract: A memory management sub-system includes code executable by a processor fir performing selecting a plurality of contexts, and selecting a sample of the separately allocable portions of an address space for each of the contexts. For each of the selected allocable portions, a corresponding portion of the host memory to which the selected allocable portion is mapped is determined, and a count corresponding to a number of separately allocable portions of any context that are commonly mapped to the corresponding portion of the host memory. For each context, a metric is computed that is a function of the counts for that context. Host memory is allocated among the contexts at least in part based on their respective metrics.

Abstract: Embodiments of the present invention provide a system that selectively performs lookups for cache lines. During operation, the system by maintains a lower-level cache and a higher-level cache in accordance with a set of rules that dictate conditions under which cache lines are held in the lower-level cache and the higher-level cache. The system next performs a lookup for cache line A in the lower level cache. The system then discovers that the lookup for cache line A missed in the lower-level cache, but that cache line B is present in the lower-level cache. Next, in accordance with the set of rules, the system determines, without performing a lookup for cache line A in the higher-level cache, that cache line A is guaranteed not to be present and valid in the higher-level cache because cache line B is present in the lower-level cache.

Abstract: A method, apparatus, and article of manufacture are provided to support dynamic assignment of data from a continuous stream of data to one or more storage devices in a storage network. The storage network is configured with one or more tiers in a hierarchy, with at least one storage device in each tier. Similarly, the storage network is in communication with both a storage manager and a data manager. The storage manager sorts the storage devices, maintains a demand function of each device, and calculates a burn rate for each storage device. The data manager is in communication with the storage manager and assigns data from the received stream of data to at least one of the storage devices.

Abstract: A method of wear leveling for a non-volatile memory is disclosed. A non-volatile memory is divided into windows and gaps, with each gap between two adjacent windows. The windows comprise physical blocks mapped to logical addresses, and the gaps comprise physical blocks not mapped to logical addresses. The windows are shifted through the non-volatile memory in which the mapping to the physical blocks in the window to be shifted is changed to the physical blocks in the gap.

Abstract: A log-based FTL and an operating method thereof for improving performances of reading and writing operations to increase the lifetime of a flash memory. In the method, when a reading operation for an LBN and an LPN is requested, a PBN and a PPN corresponding to the LBN and the LPN are calculated with reference to a pagemap corresponding to the LBN. A physical page of a physical block corresponding to the PBN and the PPN is accessed so that a reading operation is performed. On the other hand, when a writing operation for the LBN and the LPN is requested, a PBN and a PPN for a free-page of a physical block last assigned for the LBN are calculated with reference to a blockmap. The physical page of the physical block corresponding to the PBN and the PPN is accessed, so that a writing operation is performed. The pagemap stores a PBN and a PPN, and the blockmap stores a PBN list and a PPN.

Abstract: A method of managing a memory resource is provided for the storage of a plurality of sequentially received data elements, each data element comprising a plurality of data integers, the method comprising prior to storing a received data element, checking if the available storage capacity of the memory resource is less than a predetermined threshold value and in response to the available storage capacity being less than the predetermined threshold value, deleting at least one data integer from at least one of the data elements stored in the memory resource.