Patents Examined by Chae M Ko
  • Patent number: 11567839
    Abstract: Embodiments described herein detect data corruption in a distributed data set system. For example, a system comprises node(s) for processing queries with respect to a distributed data set comprising a plurality of storage segments. A write transaction resulting from a query with respect to a particular storage segment is logged in a log record that describes a modification to the storage segment. A log service provides the log record to a data server managing a portion of the distributed data set in which the storage segment is included, which performs the write transaction with respect to the storage segment. For redundancy purposes, the data server has replica(s) that manage respective replicas of the portion of the distributed data set managed thereby. For backup purposes, snapshots of the replica(s) are periodically generated. To determine a data corruption, a snapshot of one replica is cross-validated with a snapshot of another replica.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: January 31, 2023
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Alexander Budovski, Cristian Diaconu, Sandeep Lingam, Alejandro Hernandez Saenz, Naveen Prakash, Krystyna Ewa Reisteter, Rogerio Ramos, Huanhui Hu, Peter Byrne
  • Patent number: 11556261
    Abstract: A method includes writing, to a first sub-set of memory blocks of a first plane associated with a memory device, first data corresponding to recovery of an uncorrectable error and writing, to a first sub-set of memory blocks of a second memory plane associated with the memory device, second data corresponding to recovery of the uncorrectable error. A relative physical location of the first sub-set of memory blocks of the first memory plane and a relative physical location of the first sub-set of memory blocks of the second memory plane are a same relative physical location with respect to the first memory plane and the second memory plane.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: January 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ting Luo, Chun Sum Yeung, Xiangang Luo
  • Patent number: 11550660
    Abstract: A method includes providing an interposition driver, and context switching into a kernel associated with a persistent memory using the interposition driver to create a consistent view of the persistent memory.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: January 10, 2023
    Assignee: Red Hat, Inc.
    Inventor: Jeffrey E. Moyer
  • Patent number: 11544226
    Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. A plurality of failure resilient address spaces are distributed across the plurality of storage devices such that each of the plurality of failure resilient address spaces spans a plurality of the storage devices. The plurality of computing devices maintains metadata that maps each failure resilient address space to one of the plurality of computing devices. The metadata is grouped into buckets. Each bucket is stored in a group of computing devices. However, only the leader of the group is able to directly access a particular bucket at any given time.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: January 3, 2023
    Inventors: Maor Ben Dayan, Omri Palmon, Liran Zvibel
  • Patent number: 11543975
    Abstract: The present technology relates to an electronic device. The storage device according to the present technology may include a memory device and a memory controller. The memory device may include a plurality of memory blocks. The memory controller may control the memory device to perform a recovery operation for a first sudden power off on a target block on which a program operation is stopped due to the first sudden power off among the plurality of memory blocks, and perform a program operation of storing lock data including information indicating completion of the recovery operation for the first sudden power off in a page next to a page on which the recovery operation is completed in the target block.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: January 3, 2023
    Assignee: SK hynix Inc.
    Inventors: Ji Yeun Kang, Won Hyoung Lee
  • Patent number: 11537484
    Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sri Rama Namala, Lu Tong, Kristopher Kopel, Sheng-Huang Lee, Chang H. Siau
  • Patent number: 11531606
    Abstract: A memory apparatus comprising: a cell array comprising multiple first and second word lines, a fuse array configured to substitute a selection word line of the multiple first word lines with the multiple second word lines, a fail determination unit configured to determine, as a fail word line, a word line matched with a first condition during an access operation for the multiple first word lines and to determine a fail grade of the fail word line based on a second condition, an information storage unit configured to store a physical address, fail grade and access count of the fail word line as determination information for the fail word line, and a rupture operation unit configured to select the selection word line from the fail word lines based on a result of the analysis of the determination information, and perform rupturing the selection word line into the fuse array.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: December 20, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyung Sup Kim
  • Patent number: 11520651
    Abstract: A tool may identify and revert changes that caused network hardware components or hardware servers to malfunction. The tool builds and maintains a graph that represents the hardware components and servers in the system and their dependencies. When a change is made to the system, links and weights in the graph are adjusted to account for the changes. When a component or server is reported as malfunctioning, the tool traverses the graph to locate the changes that are the most likely root causes of the malfunction. The tool may then revert the change to resolve the malfunction.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: December 6, 2022
    Assignee: Bank of America Corporation
    Inventors: Surina Puri, Asif Ahmad Bala, Arjun Thimmareddy
  • Patent number: 11513971
    Abstract: An address mapping method of a storage device which includes a plurality of sub-storage devices each including an over-provision area includes detecting mapping information of a received logical address from a mapping table, selecting a hash function corresponding to the received logical address depending on the mapping information, selecting any one, which is to be mapped onto the received logical address, of the plurality of sub-storage devices by using the selected hash function, and mapping the received logical address onto the over-provision area of the selected sub-storage device. The selected hash function is selected from a default hash function and a plurality of hash functions to provide a rule for selecting the any one of the plurality of sub-storage devices.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: November 29, 2022
    Inventors: Keonsoo Ha, Minseok Ko, Hyunjoo Maeng, Jihyung Park
  • Patent number: 11507482
    Abstract: Technology is disclosed for recovering the consistency of a RAID (Redundant Array of Independent Disks) metadata database when data corruption is detected in the RAID metadata database. The RAID metadata database includes super sectors, stage sectors, and a data region. Valid data within the data region is a contiguous set of sectors extending from a head sector to a tail sector. In response to data corruption in one of the two super sectors, a set of pointers contained in the other super sector is used to identify the head sector and tail sector. In response to data corruption in both super sectors, the head sector and tail sector are located based on the contents of the sectors in the data region. Techniques are also disclosed for recovering consistency when the data corruption occurs in the stage sectors and/or data region.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: November 22, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Charles Ma, Shaoqin Gong, Geng Han, Vamsi K. Vankamamidi, Shuyu Lee, Ping Ge, Jian Gao
  • Patent number: 11500711
    Abstract: A system may include a graphics processing unit (GPU) and a processor. The GPU may include a GPU core and non-error-detection-and-correction (non-EDAC) graphics memory. The graphics memory may contain a data object and a copy of the data object. The processor may be configured to: instruct the GPU to handle the data object and the copy of the data object as textures; and instruct the GPU to execute a texture comparison shader program. The GPU core may be configured to: execute the texture comparison shader program; compare the data object and the copy of the data object; generate comparison results; and output the comparison results as pixels to an off-screen area of a framebuffer. The processor may further be configured to: obtain (a) a hash value of the off-screen area, or (b) the off-screen area; and determine whether the comparison results are at least one expected value.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: November 15, 2022
    Assignee: Rockwell Collins, Inc.
    Inventors: Marcin Kolesinski, Victor Ashby
  • Patent number: 11487663
    Abstract: In a method of operating a storage device including a plurality of disks, the plurality of disks is divided into a plurality of journal areas and a plurality of data areas, respectively. When a write command for target disks among the plurality of disks is received, a first write operation is performed to store target data to be written into journal areas of the target disks. The target disks are included in a same array. After the first write operation is completed, a second write operation is performed to store the target data into data areas of the target disks.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: November 1, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Myung Lee, Seung-Uk Shin, Jin-Young Choi
  • Patent number: 11488175
    Abstract: In various example embodiments, a system and method for a proactive customer support system are provided. In some example embodiments, outgoing communications from an application server to a client device are monitored for error messages, outgoing error messages are detected, an error type for an error message is determined, an issue ticket including the error message and the error type is generated, and instructions are transmitted that cause a customer service device to display the issue ticket. In some example embodiments, the system additionally assigns a priority score and ranks open error tickets based on their respective error messages. In some example embodiments, the system provides a help message to the client device based on the error message, receives an information request from the client device, determines a reply message based on the information request, and transmits instructions to the client device to display the reply message.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: November 1, 2022
    Assignee: eBay Inc.
    Inventor: Dileep Kumar Basam
  • Patent number: 11474901
    Abstract: A subset of drives with protection groups that have D data members and P parity members is created with (D+P+1) drives each having (D+P) partitions. One of the protection groups is used for spare capacity. (D+P) sequentially numbered protection groups are created by distributing protection group members such that members of protection group (X+Y) modulo (D+P+1) are located on the partition at drive X of partition Y. Alternatively, members of protection group (X?Y) modulo (D+P+1) are located on the partition at drive X of partition Y. New drives are added in single drive increments. When a new drive is added the first (D+P) protection group members of the lowest numbered unrotated partition of the (D+P) lowest numbered drives are rotated onto the new drive. Members are rotated in ascending order by drive to locations in ascending order by partition. A new protection group is created in the partitions made available due to rotation.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: October 18, 2022
    Assignee: DELL PRODUCTS L.P.
    Inventor: Kuolin Hua
  • Patent number: 11474920
    Abstract: Data protection systems and techniques that include: receiving data for storage in a non-volatile memory (NVM) array having a total number of physical packages that includes a number of spare physical packages, wherein each one of the physical packages is mapped to one of a plurality of logical packages; storing a respective portion of component codewords on the non-spare physical packages; and in response to one of the non-spare physical packages failing, dynamically remapping the failed physical package to one of the logical packages mapped to one of the available spare physical packages. In an aspect, reading at least the failed physical package and inserting virtual zeros into the respective portion of the component codewords corresponding to the failed physical package; performing erasure decoding to recover the data from the failed package; and rewriting the recovered data from the failed package into the one of the available spare physical packages.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: October 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Charalampos Pozidis, Thomas Mittelholzer, Nikolaos Papandreou, Milos Stanisavljevic
  • Patent number: 11467904
    Abstract: A storage system including a storage controller and a plurality of storage drives generates parity data from data. Data and parity data configure a stripe. A plurality of stripes configure a parity group allocated with a plurality of storage drives to store the parity group. A first parity group allows the number of storage drives allocated to the parity group to be equal to the number of data pieces configuring each stripe. A second parity group allows the number of storage drives allocated to the parity group to be larger than the number of data pieces configuring each stripe and allows data for each stripe to be distributed and stored in different combinations of storage drives. When the first parity group is converted to the second parity group, a storage drive is added so that it is allocated to the parity group. Data is moved to ensure a free area.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: October 11, 2022
    Assignee: HITACHI, LTD.
    Inventors: Takeru Chiba, Hiroki Fujii, Yoshiaki Deguchi
  • Patent number: 11467909
    Abstract: A Peripheral Component Interconnect Express (PCIe) interface device coupled to an external device through a link including a plurality of lanes according to the present disclosure includes an EQ controller controlling the PCIe interface device to perform an equalization operation for determining a transmitter or receiver setting of each of the plurality of lanes, and an EQ information storage storing log information indicating a number of equalization operation attempts with respect to each of a plurality of EQ coefficients and storing error information about an error occurring in an LO state with respect to each of the plurality of EQ coefficients, which includes a transmitter coefficient or a receiver coefficient, wherein the EQ controller determines a final EQ coefficient using the log information and the error information.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: October 11, 2022
    Assignee: SK hynix Inc.
    Inventors: Yong Tae Jeon, Dae Sik Park
  • Patent number: 11455221
    Abstract: A memory includes an error detection circuit that identifies a faulty feature in an array of memory cells within the memory. A redundancy enable circuit functions to replace the faulty feature with a redundant feature. The error detection circuit and the redundancy enable circuit function concurrently with a read operation on the array of memory cells.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: September 27, 2022
    Assignee: QUALCOMM Incorporated
    Inventor: Praveen Raghuraman
  • Patent number: 11455250
    Abstract: An event that indicates unexpected shutdown of a hard disk drive is determined. The hard disk includes first and second controllers that control respective first and second independently-operable actuators. Each of the actuators has one or more heads that access one or more spinning disks of the hard disk drive. While receiving power for the hard disk drive via back-electromotive force of a motor driven by the one or more spinning disks in response to the event, the first and second controllers independently move the respective first and second actuators to safe positions. In response to determining the first and second actuators are in safe positions, write cache data associated with the first and second controllers is written to a non-volatile memory.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: September 27, 2022
    Assignee: Seagate Technology LLC
    Inventors: Bryce L. DeClercq, Steven Faulhaber, Christopher L. Hill, David P. Bremer, Steven Jerome Spaulding
  • Patent number: 11442809
    Abstract: User data units are received at a memory controller to be written to a RAID strip in non-volatile memory. A first parity value is calculated for the user data units using a first parity calculation. A second parity value different from the first parity value is also calculated for the plurality of user data units using a second parity calculation. The first parity value is stored in a first parity data unit in the non-volatile memory and the second parity value is stored in a second parity data unit in the non-volatile memory. Recovery from a failure of up to two data units thus enabled by recalculating the value of the failed data units based on one or more of the first parity data unit, the second parity data unit, and the values of other user data units of the plurality of data units.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: September 13, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: Phong Sy Nguyen