Patents Examined by Chameli Chaudhuri Das
  • Patent number: 6341371
    Abstract: A method, computer system and article of manufacture for optimizing a computer program, the method comprising the steps of executing an application program and profiling selected loops of the executing program. Characteristics of the profiled loops are then compared to corresponding predetermined threshold values and the results of the comparison are used to select an optimization to be applied to subsequent execution of the selected loops. In a preferred embodiment, the optimization is the selection of either a parallel version or a serial version of the loop. Further embodiments provide for the selection of the number of processors for parallel implemented loops and for the selection of an unroll factor in serially implemented loops.
    Type: Grant
    Filed: February 23, 1999
    Date of Patent: January 22, 2002
    Assignee: International Business Machines Corporation
    Inventor: Sudarsan Tandri
  • Patent number: 6338160
    Abstract: An implementation of Java is disclosed in which references to the constant pool are implemented by using a Data Resolution Field within the constant pool entry. The Data Resolution Field acts as an index to a jump table to jump to resolve the reference or to perform the bytecode instruction. When the reference is resolved, the contents of the Data Resolution Field in the constant pool entry are modified so that the next time the bytecode is run, the resolution steps need not be done.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: January 8, 2002
    Assignee: Nazomi Communications, Inc.
    Inventors: Mukesh K. Patel, Chitrabhanu Dasgupta
  • Patent number: 6324684
    Abstract: A processor (16) is disclosed that has real-time execution control for debug functions. The processor (16) includes processor circuitry operable to execute embedded code (19) where the embedded code includes background code and foreground code. The processor (16) also includes debug circuitry interfacing with the processor circuitry and operable to communicate with a debug host (12). The debug circuitry is operable to receive a debug halt command from the debug host (12). After receipt of the debug halt command, the processor circuitry is operable to suspend execution of the embedded code (19) to allow debug of the embedded code (19). The processor circuitry is further operable, while execution of the embedded code (19) is suspended, to respond to an enabled interrupt by executing foreground code associated with the enabled interrupt.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: November 27, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: David R. Matt, Gary L. Swoboda, Karthikeyan Madathil
  • Patent number: 6292939
    Abstract: Unnecessary barrier instructions are dynamically reduced in a parallel processing object program, program module or object code section to be parallel processed in a multiprocessor system by a compiler that generates the parallel processing object program from a source program. The compiler divides the source program into parallel processing objects, issues a pre dynamic barrier instruction having parameters for barrier necessity determination that describe a first variable or array memory reference in the parallel processing object, which includes a parallel processing loop. In addition, the compiler issues a post dynamic barrier instruction having information in parameters about a second variable or array (or group of arrays) to be referenced after the parallel processing object.
    Type: Grant
    Filed: March 11, 1999
    Date of Patent: September 18, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiro Itou, Kei Nakajima
  • Patent number: 6269477
    Abstract: A computer system for establishing a program image layout of a computer program. The computer program has basic blocks that each have temporal usage vector indicating time intervals during which the basic block was accessed during an execution of the computer program. For each of the basic blocks, the layout system initializes a cluster to contain that basic block and the layout system repeats the following until one cluster remains that contains all of the basic blocks. For each possible ordered pair of clusters, the layout system determines a metric value for the ordered pair of clusters, the metric value being derived from the temporal usage vectors of the basic blocks of the cluster and estimating an effect on the performance of the computer program when that ordered pair of clusters are position in the program image in that order and contiguously. The layout system then selects the ordered pair whose metric value estimates the smallest effect on the performance of the computer program.
    Type: Grant
    Filed: September 16, 1997
    Date of Patent: July 31, 2001
    Assignee: Microsoft Corporation
    Inventors: Robert P. Fitzgerald, John W. Miller, John R. Douceur
  • Patent number: 6269475
    Abstract: An object oriented program editor operative on a text source in a language having syntax properties having a lexical analyzer, a parser, a codeblock generator and a graphical user interface. The lexical analyzer identifies language tokens in the text source. The parser which is coupled to the lexical analyzer associates syntax properties with the tokens. The codeblock generator which is coupled to the parser, groups tokens into a tree of codeblocks. The graphical user interface receives and implements user modifications of the codeblocks in a manner consistent with the programming language. A system for generating source code in a program language with respect to an object model having a plurality of classes and relations among such classes having a class selection interface, an action selection interface and a source code generator. The class selection interface is used for user selection of a chosen class.
    Type: Grant
    Filed: June 2, 1998
    Date of Patent: July 31, 2001
    Assignee: Webgain, Inc.
    Inventors: Edward J. Farrell, Neeraj Sangal
  • Patent number: 6256780
    Abstract: An assembly method and system for assembling components into an assembly. An assembly provides connectors through which the components can be exported and through which an external entity can be imported. An exported component can be connected to another assembly by importing that exported component into that other assembly. A connector can both expose components to be exported and expose connections through which an external entity can be imported. The assembly provides a mechanism through which the connectors can be exposed to external entities. An external entity can use the connector providing mechanism to retrieve a connector and then use the retrieved connector to export components and establish connections by importing external entities. In addition, the use of a standard connector and of a standard connector providing mechanism allows predefined components to be assembled into assemblies that can expose certain behavior of the components through the connectors in a predefined manner.
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: July 3, 2001
    Assignee: Microsoft Corp.
    Inventors: Antony S. Williams, Walter L. Hill, Mark B. Grossman, Crispin Goswell, Craig H. Wittenberg
  • Patent number: 6249906
    Abstract: Current software technology entails writing application programs in a high level language intended to facilitate portability to different computer processor platforms. Because the program is portable, the resulting object code is not tailored to run as efficiently as possible on the particular computer processor platform. Manually tuning a specific application program may be done, but it is time consuming and is rarely done by the end user. The disclosed invention provides an automated method of tuning application programs to execute more efficiently.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: June 19, 2001
    Assignee: International Business Machines Corp.
    Inventors: Frank Eliot Levine, Charles Philip Roth
  • Patent number: 6240548
    Abstract: Methods and apparatus for dynamically compiling byte codes associated with methods during idle periods in the execution of a computer program are disclosed. The described methods are particularly suitable for use in computer systems that are arranged to execute both interpreted and compiled byte codes. In some embodiments, methods to be dynamically compiled are referenced in one or more lists. The lists may be prioritized to facilitate the compilation of the highest priority methods first. In one embodiment, a pair of compilation lists are provided with a first one of the compilation lists being created prior to processing the computer program while the other is created during the processing of the computer program.
    Type: Grant
    Filed: July 14, 1999
    Date of Patent: May 29, 2001
    Assignee: Sun Microsystems, Inc.
    Inventors: Urs Hölzle, Lars Bak
  • Patent number: 6230317
    Abstract: A method for executing software pipelined executable code generated by compiling a set of unexecutable instructions having an inner loop and an outer loop is disclosed. Instructions are executed that perform the operations specified in the outer loop using a first storage area. A second storage area is allocated for use when performing the operations specified in the inner loop. Instructions are then executed that perform the operations specified in the inner loop using the second storage area, wherein at least certain storage locations in the first storage area are not alterable while the operations specified in the inner loop are being performed.
    Type: Grant
    Filed: July 11, 1997
    Date of Patent: May 8, 2001
    Assignee: Intel Corporation
    Inventor: Youfeng Wu
  • Patent number: 6223344
    Abstract: The present invention provides a method and apparatus for versioning persistent objects which updates the version of a persistent object by splitting the persistent object up into two sections, a header section and a data section. The header section has a data pointer to the data section. The header section determines the object identity of the persistent object and always remains in place. Since the header section of the object always remains intact, the object identity of the persistent object never changes. When updating the version of the persistent object, the persistent object versioning mechanism simply updates the pointer in the header section of the object to reference a newly created data section. Once the persistent object versioning mechanism updates the data pointer to reference the new data section, existing objects can reference the new version of the persistent object using the original object identity of the persistent object.
    Type: Grant
    Filed: June 11, 1998
    Date of Patent: April 24, 2001
    Assignee: Internationl Business Machines Corporation
    Inventors: Scott Neal Gerard, Steven Lester Halter, Steven J. Munroe, Erik E. Voldal
  • Patent number: 6223340
    Abstract: A dynamic compiler determines whether to inline methods in place of virtual method calls by inspecting such calls' receiver expressions. If a given call site meets other criteria for inlining, the method is inlined if its receiver expression can be proved to have a property called “pre-existence.” One kind of expression whose pre-existence is easily proved is a calling-procedure argument to which the body of the calling procedure makes no assignment. One of the other criteria is that the argument's static type is a class whose definition of the callee method has not been overridden, and the compiler employs a dependency data structure to record against both the caller and the callee that the caller contains code whose validity depends on the assumption that this criterion has been met.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: April 24, 2001
    Assignee: Sun Microsystems, Inc.
    Inventor: David L. Detlefs
  • Patent number: 6182286
    Abstract: A dynamic versioning system for synchronizing different versions of modules among different versions of a complex multi-module software system, and maintaining a consistent view of a version of the complex system for each user having access to the system. The dynamic versioning system grants a user read-only access to the multiple modules in a complex system, and promotes the access to write access only when a user is ready to save a modified module in the permanent non-volatile memory of the complex system. The dynamic versioning system manages the evolving versions of the complex system with a Dynamic Versioning Table (DVT) and master modules that identify the multiple slave modules associated with a particular version of the complex system. Old versions of modules are removed from the complex system's permanent non-volatile memory when the last user has terminated use of the complex system.
    Type: Grant
    Filed: December 28, 1998
    Date of Patent: January 30, 2001
    Assignee: Microsoft Corporation
    Inventors: Andrew David Sigal, Daniel Bien, Augusto Pissarra
  • Patent number: 6173445
    Abstract: A method of displaying information to a user upon startup of a program on a first computer. The method includes obtaining the information from a second computer and, upon startup of the program on the first computer, displaying the information. A method is described, where the program is a program that runs on a first computer. A second computer sends, over the network to first computer, information to be displayed to a user. A command is received to launch the program. After receiving the command to launch the program and without user intervention, at least a portion of the information is displayed. Without user intervention, the at least a portion of the information is removed. A method, wherein the information is obtained over a network is described, as well as wherein the network comprises the internet. An embodiment wherein the information is described in a flash screen is described.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: January 9, 2001
    Inventors: Nicholas Robins, Thomas Chipperfield
  • Patent number: 6161217
    Abstract: A computer system (10) is configured as a compiler to translate source code (FIG. 4) into object code (FIG. 6). The source code calls a polymorphic method on a receiver object. The compiler inlines the polymorphic method and guards the inlining with guard code that causes the executing microprocessor to skip the inlining in favor of a virtual method call when it determines that the inlined code is not appropriate for the receiver object. To make that determination, the guard code compares the address of the method version that has been inlined with the receiver object's pointer to its version of the polymorphic method.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: December 12, 2000
    Assignee: Sun Microsystems, Inc.
    Inventors: David L. Detlefs, Ole Agesen
  • Patent number: 6083280
    Abstract: A method for increasing a relative efficiency of an automatic data processing system involving a processing sequence of a plurality of event types. The method includes the steps of measuring event activity of each event type of the plurality of event types and ordering the processing sequence of at least a first set of the event types of the plurality of event types based upon the measured event activity.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: July 4, 2000
    Inventor: Robert T. Eitel
  • Patent number: 6075942
    Abstract: A first computer system (34) compiles a source program into machine code for a register-oriented microprocessor, optimizing the global allocation of microprocessor registers in the process. It then translates the resultant code into generic-machine operand-stack-oriented code. In performing the translation, it generates code that preserves the register-oriented code's microprocessor-register allocation by filling the operand stack from local variables chosen in accordance with a predetermined correspondence between local variables and microprocessor registers. That code also stores the operand stack's contents in accordance with that same correspondence. A second computer system (32), which employs the register-oriented microprocessor, converts the resultant generic machine code into its own machine code in accordance with the same association between local variables to microprocessor registers.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: June 13, 2000
    Assignee: Sun Microsystems, Inc.
    Inventor: Robert S. Cartwright, Jr.
  • Patent number: 6055369
    Abstract: An apparatus is disclosed for visual programming for creating a program with a visual user interface. The visual programming apparatus has a screen storage unit for storing multiple screens to be employed with the program; a screen creating unit for creating the multiple screens to be employed with the program and storing the multiple screens in the screen storage unit; a screen flow creating unit for creating a screen flow indicating a flow of processes by displaying on an edit screen the multiple screens stored in the screen storage unit in a compressed manner and specifying a link between the multiple compressed screens on the edit screen; a screen flow information extracting unit for extracting data of a link from the screen flow created by the screen flow creating unit; and a code creating unit for creating a source code from the data of the link extracted by the screen flow information extracting unit and from data of the screen.
    Type: Grant
    Filed: May 6, 1997
    Date of Patent: April 25, 2000
    Assignees: Hitachi Software Engineering Co., Ltd., Regents of the University of Minnesota
    Inventors: Tomoharu Sawahata, Wei-Tek Tsai, Akira K. Onoma, Tao Jiang
  • Patent number: 6052530
    Abstract: A dynamic translation system is configured to translate existing code into translated code which is compatible with a particular computer system. As the dynamic translation system translates the existing code, the computer system executes the translated code. Once a synchronous fault occurs, the dynamic translation system retranslates the block of code containing the synchronous fault and saves the instruction and state mappings for each instruction capable of causing the synchronous fault. Once the instruction causing the synchronous fault is reached during the retranslation process, the dynamic translation system combines the saved instruction and state mappings of the instruction causing the synchronous error with the current machine state of the computer system to form a simulated machine state. This simulated machine state represents the machine state that would have existed at the time of the synchronous fault if the original code were executing, instead of the translated code.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: April 18, 2000
    Assignee: Hewlett-Packard Co.
    Inventors: William B. Buzbee, James S. Mattson, Lacky V. Shah, David A. Dunn
  • Patent number: 6049667
    Abstract: A computer system, method of compiling, and method of accessing an address space utilize a data representation of a pointer that is smaller than the width of the address space during runtime of a computer program to retrieve a selected memory address in the address space whenever an access to the address space is required. For uses of the pointer that do not require an access to the address space, such as many arithmetic operations, the smaller data representation of the pointer is used. Compilation of a computer program including a reference to a pointer results in the generation of mapping code that generates a data representation of a pointer that is mapped to a selected memory address in the address space during execution of the computer program.
    Type: Grant
    Filed: August 15, 1997
    Date of Patent: April 11, 2000
    Assignee: International Business Machines Corporation
    Inventor: Cary Lee Bates