Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate, a pixel defining layer and at least one photo spacer. The pixel defining layer is disposed on the base substrate and includes a plurality of openings, the at least one photo spacer is disposed on a side of the pixel defining layer away from the base substrate. A distance from any point at a bottom of the at least one photo spacer contacting the pixel defining layer to an upper edge of a side wall of the plurality of openings is greater than or equal to 5 ?m.

Abstract: The present invention provides a display panel, a manufacturing method thereof, and a display device. The display panel includes power line layer. The power line layer includes a first power line layer and a second power line layer, and the second power line layer is electrically connected to the first power line layer. The first power line layer extends toward a first side surface of the substrate and is bent along the first side surface to a side of the substrate away from the second power line layer. A first circuit board is disposed on a side of the substrate away from the second power line layer, and the first circuit board is electrically connected to the first power line layer.

Abstract: An integrated circuit device includes: a semiconductor on insulator (SOI) substrate layer including a base substrate layer, an insulating substrate layer, and a cover substrate layer; a semiconductor substrate layer; a plurality of first fin-type active areas and a plurality of second fin-type active areas each defined by a plurality of trenches, and extending in a first horizontal direction, in above the SOI substrate layer and the semiconductor substrate layer, respectively; a plurality of nanosheet stacked structures comprising nanosheets extending in parallel with each other and spaced apart from upper surfaces of the plurality of first fin-type active areas and the plurality of second fin-type active areas; a plurality of first source/drain regions extending into the SOI substrate layer; and a plurality of second source/drain regions extending into the semiconductor substrate layer. Lower surfaces of the first and second source/drain regions may not be coplanar with each other.

Abstract: A spin-orbit-torque (SOT) magnetic device includes a bottom metal layer, a first magnetic layer disposed over the bottom metal layer, a spacer layer disposed over the first magnetic layer, and a second magnetic layer disposed over the spacer layer. A diffusion barrier layer for suppressing metal elements of the first magnetic layer from diffusing into the bottom metal layer is disposed between the bottom metal layer and the first magnetic layer.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and nanostructures suspended over the substrate. The semiconductor structure also includes a gate structure wrapping around the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure also includes a contact vertically over the source/drain structure and a first conductive structure vertically over the gate structure. The semiconductor structure also includes a second conductive structure in contact with a top surface of the first conductive structure and a top surface of the contact and including an extending portion laterally sandwiched between the first conductive structure and the contact.

Abstract: A semiconductor device which has favorable electrical characteristics, a method for manufacturing a semiconductor device with high productivity, and a method for manufacturing a semiconductor device with a high yield are provided.

Abstract: A semiconductor device includes a base, a first FET that includes at least two channel structure portions laminated, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2?(L1/2) is satisfied.

Abstract: A semiconductor device structure is provided. The device includes a plurality of semiconductor layers and a gate electrode layer surrounding each semiconductor layer of the plurality of semiconductor layers. The gate electrode layer includes a first part, and a second part below the first part, the second part comprises a first portion, wherein an exterior surface of the first portion has a first radius of curvature, and a second portion below the first portion, and a third portion below the second portion, wherein an exterior surface of the third portion having a second radius of curvature different than the first radius of curvature.

Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, and a source/drain (S/D) region adjacent to the gate structure. The S/D region can include first and second side surfaces separated from each other. The S/D region can further include top and bottom surfaces between the first and second side surfaces. A first separation between the top and bottom surfaces can be greater than a second separation between the first and second side surfaces.

Abstract: A semiconductor structure includes a substrate and an array of two-port (TP) SRAM cells. Each TP SRAM cell includes a write port and a read port. The array includes first and second TP SRAM cells. The write ports of the first and second TP SRAM cells abut each other. The write port of the first TP SRAM cell includes a first write pull-down (W_PD) transistor. The write port of the second TP SRAM cell includes a second W_PD transistor. The array of TP SRAM cells further includes a first source/drain contact landing on both a source/drain electrode of the first W_PD transistor and another source/drain electrode of the second W_PD transistor. The first TP SRAM cell includes a first Vss conductor located at a first metal layer. The first Vss conductor is directly above the first source/drain contact and connected to the first source/drain contact.

Abstract: A device includes a first semiconductor fin, a second semiconductor fin, a source/drain epitaxial structure, a semiconductive cap, and a contact. The first semiconductor fin and the second semiconductor fin are over a substrate. The source/drain epitaxial structure is connected to the first semiconductor fin and the second semiconductor fin. The source/drain epitaxial structure includes a first protruding portion and a second protruding portion aligned with the first semiconductor fin and the second semiconductor fin, respectively. The semiconductive cap is on and in contact with the first protruding portion and the second protruding portion. A top surface of the semiconductive cap is lower than a top surface of the first protruding portion of the source/drain epitaxial structure. The contact is electrically connected to the source/drain epitaxial structure and covers the semiconductive cap.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. Further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. A backside contact is arranged below and coupled to the first source/drain region. The backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact.

Abstract: A light-emitting device comprises a substrate comprising a top surface; a plurality of light-emitting units formed on the top surface of the substrate comprising a first light-emitting unit, a second light-emitting unit, and one or a plurality of third light-emitting units, wherein each of the plurality of light-emitting units comprises a first semiconductor layer, an active layer and a second semiconductor layer; an insulating layer comprising a first insulating layer opening and a second insulating layer opening formed on each of the plurality of light-emitting units; a first extension electrode covering the first light-emitting unit, wherein the first extension electrode covers the first insulating layer opening on the first light-emitting unit without covering the second insulating layer opening on the first light-emitting unit; a second extension electrode covering the second light-emitting unit, wherein the second extension electrode covers the second insulating layer opening on the second light-emittin

Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.

Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Abstract: A method of forming alignment marks includes providing a III-V compound substrate having a device region and an alignment mark region, forming a hardmask layer having a first set of openings on the alignment mark region exposing a first surface portion of the III-V compound substrate and a second set of openings on the device region exposing a second surface portion of the III-V compound substrate, etching the exposed surface of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches, and epitaxially regrowing a semiconductor layer in the trenches to form the alignment marks extending to a predetermined height over the processing surface of the III-V compound substrate.

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.