Abstract: The present disclosure provides an organic electroluminescent device, a display substrate including the organic electroluminescent device, and a display apparatus including the display substrate. The organic electroluminescent device includes an anode, a cathode, and a light emitting layer between the anode and the cathode, wherein a hole transport layer is provided between the anode and the light emitting layer and includes a hole transport material and a P-type doping material, electrons of the highest occupied molecular orbit of the P-type doping material are excitable to the lowest unoccupied molecular orbit of the P-type doping material under the excitation of light to cause an electron transfer reaction from the highest occupied molecular orbit of the hole transport material to the highest occupied molecular orbit of the P-type doping material.

Abstract: The present disclosure relates to package structure, packaging method and display device. A package structure comprises: a first substrate and a second substrate disposed opposite to each other, a peripheral portion of at least one of the first substrate and the second substrate being provided with a sealing hole; a first sealing structure disposed between the first substrate and the second substrate and located at a peripheral region of the first substrate; and a second sealing structure disposed in the sealing hole, wherein the first sealing structure is bonded to the second sealing structure.

Abstract: A method of making a plurality of integrated circuit (“IC”) packages includes picking up a plurality of physically unconnected IC components; and simultaneously placing each of the physically unconnected IC components on corresponding portions of an unsingulated IC package strip that includes a sheet of integrally connected leadframes.

Abstract: Light Emitting Devices (LEDs) are fabricated on a wafer substrate with one or more thick metal layers that provide structural support to each LED. The streets, or lanes, between individual LEDs do not include this metal, and the wafer can be easily sliced/diced into singulated self-supporting LEDs. Because these devices are self-supporting, a separate support submount is not required. Before singulation, further processes may be applied at the wafer-level; after singulation, these self-supporting LEDs may be picked and placed upon an intermediate substrate for further processing as required. In an embodiment of this invention, protective optical domes are formed over the light emitting devices at the wafer-level or while the light emitting devices are situated on the intermediate substrate.

Abstract: The present disclosure provides an integrated circuit with an interconnect structure and a method for forming the integrated circuit. In one embodiment, a method of the present disclosure includes receiving a workpiece that includes a first recess in a dielectric layer over the workpiece, depositing a contact fill in the first recess and over the dielectric layer to form a contact feature, planarizing a top surface of the workpiece to remove the contact fill over the dielectric layer, depositing an interlayer dielectric layer over the planarized top surface of the workpiece, forming a second recess in the interlayer dielectric layer to expose the contact fill in the dielectric layer, recessing the contact fill by soaking the workpiece in a room temperature ionic liquid, and depositing a conductive layer over the recessed contact fill. The material forming the contact fill is soluble in the room temperature ionic liquid.

Abstract: A bypass thyristor device includes a semiconductor device providing a thyristor with a cathode electrode on a cathode side, a gate electrode on the cathode side surrounded by the cathode electrode and an anode electrode on an anode side; an electrically conducting cover element arranged on the cathode side and in electrical contact with the cathode electrode on a contact side; and a gate contact element electrically connected to the gate electrode and arranged in a gate contact opening in the contact side of the cover element; wherein the cover element has a gas expansion volume in the contact side facing the cathode side, which gas expansion volume is interconnected with the gate contact opening for gas exchange.

Abstract: A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other.

Abstract: Packaging structure and method of forming a packaging structure are provided. A substrate is provided, and an adhesive layer is formed on the substrate. An improvement layer is formed on the adhesive layer. The improvement layer contains openings exposing surface portions of the adhesive layer at bottoms of the openings. A plurality of chips is provided and includes functional surfaces. The plurality of chips is mounted on the substrate such that the functional surfaces are bonded to the adhesive layer at the bottoms of the openings.

Abstract: A semiconductor device includes a semiconductor layer which has a first device formation region and a second device formation region, a first HEMT which is formed in the first device formation region and has a first two-dimensional electron gas region as a channel, a second HEMT which is formed in the second device formation region and has a second two-dimensional electron gas region as a channel, and a region separation structure which is formed in the semiconductor layer and defines the first device formation region and the second device formation region.

Abstract: A semiconductor package includes a semiconductor chip, and a connection structure disposed on at least one side of the semiconductor chip, and including an insulating layer and a redistribution layer electrically connected to the semiconductor chip, wherein the redistribution layer includes a plurality of conductive patterns, and at least two of the plurality of conductive patterns have different degrees of surface roughness, and a conductive pattern having a higher surface roughness has a width wider than a width of a conductive pattern having a lower surface roughness.

Abstract: Disclosed is a manufacturing method of a thin film transistor, comprising: sequentially preparing a gate, a gate insulation layer and an active layer on the substrate; preparing an etching stopper layer on the active layer; depositing an ohmic contact layer film on the etching stopper layer and the active layer, and depositing a source drain conductive film on the ohmic contact layer film; processing the source drain conductive film to form a source and a drain, which are patterned, and processing the ohmic contact layer film by a dry etching process to form an ohmic contact layer, which is patterned; removing the etching stopper layer after preparing the ohmic contact layer. Since the etching stopper layer is disposed above the channel of the transistor before preparing the ohmic contact layer, the damage to the active layer by dry etching can be effectively avoided to improve the performance of the transistor.

Abstract: Photodetectors and fabrication methods thereof and imaging sensors are provided. An exemplary photodetector includes a first substrate formed with pixel circuits and common electrode connection members and first wiring boards electrically connected to the corresponding pixel circuits; and a second substrate formed with pixel units and isolation wall members isolating pixel units. Each isolation wall member includes a conductive member and a sidewall; second wiring boards are formed on a front surface of the second substrate; the second wiring boards are electrically connected to first terminals of the pixel units; a transparent electrode layer is formed on a back surface of the second substrate; and a second terminal of each pixel unit is electrically connected to the transparent electrode layer. The second wiring boards are bonded and electrically connected to the first wiring boards and the transparent electrode layer is electrically connected to the common electrode connection members.

Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

Abstract: Integrated circuit substrates having through silicon vias (TSVs) are described. The TSVs are vias extending through the silicon substrate in which the integrated circuitry is formed. The TSVs may be formed prior to formation of the integrated circuitry on the integrated circuit substrate, allowing the use of via materials which can be fabricated at relatively small sizes. The integrated circuit substrates may be bonded with a substrate having a microelectromechanical systems (MEMS) device. In some such situations, the circuitry of the integrated circuit substrate may face away from the MEMS substrate since the TSVs may provide electrical connection from the circuitry side of the integrated circuit substrate to the MEMS device.

Abstract: The application discloses a light-emitting device including a carrier, a light-emitting element and a connecting structure. The carrier includes a first connecting portion and a first necking portion extended from the first connecting portion. The first connecting portion has a first width, and the first necking portion has a second width. The second width is less than the first width. The light-emitting element includes a first light-emitting layer being able to emit a first light and a first contacting electrode formed under the first light-emitting layer. The first contacting electrode is corresponded to the first connecting portion. The connecting structure includes a first electrical connecting portion and a protection portion surrounding the first electrical connecting portion. The first electrical connecting portion is electrically connected to the first connecting portion and the first contacting electrode.

Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

Abstract: A method of producing a bifacial photovoltaic cell is disclosed herein, the method comprising: a) forming an n-dopant-containing layer on a first surface of a semiconductor substrate; b) forming a boron-containing layer on a second surface of the substrate by sputtering boron and/or by boron ion implantation; and c) effecting diffusion of the n-dopant and boron into the substrate, to dope the first surface with the n-dopant and the second surface with the boron. Further disclosed herein are bifacial photovoltaic cells, as well as photovoltaic modules, power plants and electric devices comprising said photovoltaic cells, comprising a semiconductor substrate, an n+ layer on a first surface thereof and a boron-containing p+ layer on a second surface thereof, wherein a variability of boron concentration in the p+ layer is no more than 5%.

Abstract: To provide a wafer processing method which can simplify the wafer processing process and efficiently obtain chips of stable quality. A wafer processing method includes: a tape attaching step of attaching a back grinding tape to the front surface of a wafer; a modified region forming step of applying a laser beam from the back surface of the wafer along a cut line to form modified regions inside the wafer; a back surface processing step of processing the back surface of the wafer having the modified regions to reduce a thickness of the wafer; and a dividing step of, in a state in which the back grinding tape is attached to the front surface of the wafer, applying a load to the cut line from the back surface of the wafer to divide the wafer along the cut line and obtain individual chips.

Abstract: Semiconductor device structures and methods for forming the same are provided. A semiconductor device structure includes a gate structure over a semiconductor substrate. The gate structure includes a gate electrode layer and a gate dielectric layer covering a bottom surface and sidewalls of the gate electrode layer. The semiconductor device structure also includes spacer elements in contact with sidewalls of the gate structure and protruding from a top surface of the gate electrode layer. The semiconductor device structure also includes a first protection layer over the gate electrode layer and between the spacer elements. The semiconductor device structure also includes a dielectric layer over the first protection layer and between the spacer elements. A portion of the dielectric layer is between sidewalls of the spacer elements and sidewalls of the first protection layer.

Abstract: Embodiments of three-dimensional (3D) memory devices having a shielding layer and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a plurality of memory strings each extending vertically above the peripheral device, a semiconductor layer disposed above and in contact with the plurality of memory strings, and a shielding layer disposed between the peripheral device and the plurality of memory strings. The shielding layer includes a conduction region configured to receive a grounding voltage during operation of the 3D memory device.