Abstract: In some embodiments, a method receives a packet for a flow associated with a workload. Based on an indicator for the flow, the method determines whether the flow corresponds to one of an elephant flow or a mice flow. Only when the flow is determined to correspond to an elephant flow, the method enables a hardware acceleration operation on the packet. The hardware acceleration operation may include hardware operation offload, receive side scaling, and workload migration.

Abstract: Aspects relate to analog-to-digital conversion of an analog signal. The resolution (number of bits) and/or the quantization levels of the analog-to-digital conversion may be configurable. A device may configure its analog-to-digital conversion parameters. For example, a first device may reduce the number of bits for its analog-to-digital converter to reduce power consumption. In this case, the first device may transmit an indication of selected analog-to-digital conversion parameters to a second device that will transmit to the first device. In this way, the second device may take appropriate action, if needed. A device may request another device to use certain analog-to-digital conversion parameters. For example, a first device may determine that a second device should use a larger number of bits for its analog-to-digital conversion process to improve the quality of the communication between the first and second devices.

Abstract: Systems, methods, and circuitries are provided for performing sidelink communication. An example method indicates a frequency resource reservation in sidelink control information (SCI). The method includes identifying a transport block (TB) for transmission to a UE; determining a total number of sub-channels (NSL) in a resource pool for sidelink communication, a number of sub-channels (Lsub) of the TB, a first starting sub-channel index x1 of a first retransmission of the TB, and a second starting sub-channel index x2 of a second retransmission of the TB. The method includes determining a frequency resource indication value (FRIV) based on NSL, LSUB, x1, and x2, wherein the FRIV represents a result of a predetermined function of Lsub, x1, and x2 that generates a unique value for possible combinations of Lsub, x1, and x2. The FRIV is encoded in SCI and the SCI is transmitted to the UE.

Abstract: The present disclosure provides a method and a device in wireless transmission. A User Equipment (UE) first receives a first signaling, and then receives a first radio signal, the first radio signal carrying a first bit block. The first signaling is used for determining a transmission format corresponding to the first radio signal. The transmission format corresponding to the first radio signal is one transmission format in a first format set, and the first format set comprises a first transmission format and a second transmission format. A radio signal corresponding to the first transmission format includes P radio sub-signal(s), each one of the P radio sub-signal(s) carries the first bit block, and the P radio sub-signal(s) is(are) transmitted by a same antenna port group.

Abstract: One example may include a process that includes establishing a transmission control protocol (TCP) connection between a client device and a server to form a virtual private network (VPN), permitting communication between the client device and the server on the TCP connection, monitoring, via the VPN server, communication over the TCP connection to identify one or more connection parameters, establishing a second connection between the client device and the server when the one or more connection parameters indicate a slowing of the TCP connection below a threshold and below a previously measured connection rate, receiving, via the TCP connection, application data used by one of the applications operating on the client device, and receiving, via the second connection, application data used by another application of the applications.

Abstract: Embodiments herein provide methods of sidelink communication between nodes including resource selection, congestion control, and/or resource signaling. Other embodiments may be described and claimed.

Abstract: An improved circuit for compensating an input/output characteristic linearity of a parallel comparison type analog-to-digital converter which reduces a wasteful consumption of current in the linearity compensation circuit. In the improved linearity compensation circuit, a dummy circuit having the same construction as a bias circuit of each comparator of the A/D converter is installed for providing a current I.sub.E which is an amplification of an input current by means of the input circuit of each comparator, a first current multiplier is installed for providing a multiplied current kI.sub.E on the basis of the current provided by the dummy circuit, an amplifier is installed for providing a current ki which corresponds to a multiplication of the current i by an amplification factor of the input circuit, and a second current multiplifier is installed for providing another multiplied current kli which is a multiplication of the current ki by l.

Abstract: A method and apparatus are disclosed for converting a digital TACAN output into an analog potentiometer input suitable for an analog navigation computer. The apparatus includes an input register for temporarily storing a digital TACAN output signal. A nines complement generation circuit is utilized to generate the nines complement of the digital TACAN output signal and the nines complement is temporarily stored in a second register. The data in each register is then utilized to control one of two identical resistive circuits which are coupled to a common output node so that the total resistance in both circuits is always equal to a selected total resistance. In a preferred embodiment of the present invention, a plurality of optically coupled solid state relays are utilized to control the resistive circuits.

Abstract: An analog output system coupled to a digital system bus (1, FIG. 1) comprises a RAM (8) in which digital data may be input from the system bus. The data is converted into analog form by digital-to-analog converters (30-37) in either continuous mode or intermittent mode, depending upon the contents of control/status register (18). The system also comprises interrupt logic (6), bus arbitration control logic (16), and reconstruction filters (40-47). A watchdog timer (50) zeroes all outputs which have not been accessed via the system bus (1) within a specified time period. The conversion rate can be controlled either by an internal timer (52) or by an external trigger (57). The output channel configuration and conversion frequency are fully software programmable.

Abstract: A rotatable member having multiple discrete positions between opposite ends of a normal path of movement is provided with two (or three) parallel, encoded tracks having different patterns of distinct, serial sections. These tracks cooperate with relatively stationary probes of a position sensor. As the rotatable member moves from position to position, the sensor will produce a family of two (or three) separate binary signals that changes states as the probes detect boundaries between successive sections of the tracks with which they respectively communicate, and the patterns of the encoded sections are so selected that the sequence of state changes when the rotatable member is approaching a predetermined mid position will differ from the sequence when the member is moving away therefrom.

Abstract: Integrated circuits in the form of a multiplexer, an instrumentation amplifier, a sample-and-hold amplifier, and an A/D converter are mounted on a single substrate, forming a data acquisition system capable of selecting one of a number of analog signals and converting it into a digital number. The resulting package is mounted in a leadless chip carrier (LCC) suitable for surface mounting.

Abstract: A communication system and method for transmitting information in the form of binary digital data to be transmitted is encoded into two separate two level sequences S1 and S2 such that the first occurrence of a logic "1" is encoded into the same level in both sequences and each subsequent occurrence of a logic "1" is encoded into the level opposite of the previous level representing a logic "1" in each of the sequences S1 and S2, and the first occurrence of a logic "0" is encoded into opposite levels in sequences S1 and S2 and every subsequent occurrence of a logic "0" is encoded into the level opposite of the previous level representing a logic "0" in each of the sequences S1 and S2. The two encoded streams drive optical signal producing means of respectively different wavelengths and the two optical signals are transmitted over a wavelength-multiplexed fiber-optic link.

Abstract: A switched capacitor circuit for use in a digital-to-analog converter, an analog-to-digital converter, or other digitally controlled circuit is disclosed. The switched capacitor circuit includes first and second arrays (30, 40) of switched capacitors of substantially identical value, each capacitor having a switched terminal. The switched capacitor circuit further includes a decoding circuit (20) responsive to a digital input having a decimal value N for providing control signals for each of the capacitor arrays. Logic circuitry (33, 43, GC(I)) responsive to the control signals is included for sequentially switching the switched terminals of L and M capacitors respectively of the first and second switched capacitor arrays in a predetermined sequence so as to maintain the geometrical centroid of the switched capacitors at a substantially constant location, where the sum of L and M is equal to N.

Abstract: For reducing the redundancy ratio of an entity key set, from very high ratios when encoded into conventional I/O code-words, down to a ratio close to zero, a non-redundant number code representation is employed in an encoder/decoder in lieu of a conventional multiple code-word representation, each member of the number code representing a member of the entity key set. Such a number code encoder/decoder may hold in store and provide access to an entity key set representing a set of 65535 different textual or lexical words, thereby using a 16 bit fixed length number code. Code-words representing such code numbers would require 16 bits of storage each if being held in store, however, such code numbers are produced using two alternative methods, (i) as relative address values of individual storage locations within a string of storage locations, e.g., a string of 8 bit byte locations, or (ii) as marked bit counts within a bit map representing the stored set.

Abstract: A data interface circuit for use when interfacing between two communication links communicating frames of digital data in PCM and ADPCM formats is provided. The data interface circuit provides control information for selecting one of a plurality of algorithms to control the transformation of data between a plurality of PCM and ADPCM formats. A single encoded control signal is utilized to establish frame boundaries and to select a predetermined one of the plurality of algorithms to use in converting between PCM and ADPCM data.

Abstract: A convertor for converting an analog signal to a digital pulse comprises a switching capacitor which is charged by a differential analog signal supplied to the switching capacitor over an input circuit. The capacitor is discharged over an output circuit with the aid of a constant current supply. The charge level of the capacitor is proportional to the analog signal so that the time it takes the capacitor to discharge to a selected low charge level, is proportional to the analog signal. This time period is used by a microprocessor control to generate a digital pulse having a pulse equal to the discharge time for the capacitor. The microprocessor also selectively connects the input and output circuits to the capacitor for respectively charging and discharging the capacitor.

Abstract: In a successive approximation analogs-to-digital converter, a successive approximation register (SAR) includes an N bit, edge triggered shift register, each bit including a master-slave flip-flop. The output of each shift register bit is applied to a latch input of a D-type latch and to one input of a two-input gate that performs a logical ANDing function. Another input of the gate is connected to an output of the latch. The D input of each of the N latches is connected to an output of a corresponding comparator, which compares an analog input signal to a signal produced by an N bit digital-to-analog converter (DAC) in response to successive approximation numbers produced by the SAR. The gate outputs are connected to digital inputs of the DAC. A "0" propagates through the shift register at the DAC conversion rate.

Abstract: A high precision analog to digital converter comprises the combination of an imperfect or low resolution digital to analog converter having an error function known in terms of orthonormal components and an error compensating device capable of generating correction terms which do not interact with one another. The correction terms are based on orthonormal components namely, the Walsh function components, of each signal level to be compensated. At most only one weighting value per bit is required, the combination of which will compensate for errors of any bit combination. In a specific embodiment employing feedback compensation, the output of the low resolution converter and of the compensating device may be summed to produce a high performance, high precision converter with increased accuracy and resolution.

Abstract: A data compaction method, for writing data in highly compact binary form in a data storage medium using a microprocessor, compresses serially occurring transaction values in a limited memory space by substituting prefix codes for previously occurring values and for commonly occurring previous values. The previous values are listed and updated on tables by the microprocessor so that they are indexed to the prefix codes adaptively to changing local values and changing common values over time. The data compaction method is particularly suitable for an account card having a limited, non-erasable memory used in an automated transaction terminal for maintaining an account record of transactions in frequently recurring amounts. A postage metering terminal is operated by the account card, in which an initial balance has been written and each purchase of postage is recorded. A current balance is recomputed by parsing the previously recorded data.

Abstract: An analog-to-digital converter (10) comprises a set of comparators (12a-12f) for providing a set of different output signals whose logic states are a function of an analog input signal voltage and one or more reference voltage signals supplied by a resistive network (16). The comparators are connected to a decoder (20) for processing the thermometer code outputs of the comparators to generate a digital word output corresponding to the voltage amplitude of the analog signal. Several of the comparators are also connected to an error checking network (22), including a preconditioning circuit (100) and a detection circuit (102) for processing these comparator outputs to provide an error signal whenever one or more of the comparators are not operating properly. The error checking network and decoder are connected to an error correction circuit (26) for correcting the digital word signal in accordance with the error signal.