Abstract: A desirable impurity, such as reactive gases and inert gases, is safely introduced into a substrate/oxide interface during high pressure thermal oxidation. Desirable impurities include chlorine, fluorine, bromine, iodine, astatine, nitrogen, nitrogen trifluoride, and ammonia. In one embodiment, the desirable impurity is introduced into a processing chamber prior to the high pressure oxidation step. Then, the temperature is brought to or maintained at an oxidation temperature. In another embodiment, the desirable impurity is introduced into the processing chamber after the high pressure oxidation step, while the temperature is still sufficiently high for oxidation. In yet another embodiment, the desirable impurity is introduced into the processing chamber both before and after the high pressure oxidation step.

Abstract: A method for fabricating wiring of a semiconductor device, which includes a first step for depositing an insulating film on a semiconductor substrate, and forming contact holes by selectively etching the insulating film, a second step for forming a barrier layer on the insulating film and the substrate, a third step for forming a first aluminum alloy layer on the barrier layer, a fourth step for forming a second aluminum alloy layer containing germanium on the first aluminum alloy layer, and a fifth step for forming an aluminum alloy wiring by annealing the substrate on which the first and the second aluminum alloy layers are formed, whereby making it possible to obtain the wiring of a semiconductor device capable of flowing at a low temperature which is the characteristic of Al--Ge wiring and capable of improving the characteristic of the electromigration of the wiring.

Abstract: A nitrogen-group III compound semiconductor satisfying the formula Al.sub.x Ga.sub.y In.sub.1-x-y N, inclusive of x=0, y=0 and x=y=0, and a method for producing the same comprising the steps of forming a zinc oxide (ZnO) intermediate layer on a sapphire substrate, forming a nitrogen-group III semiconductor layer satisfying the formula Al.sub.x Ga.sub.y In.sub.1-x-y N, inclusive of x=0, y=0 and x=y=0 on the intermediate ZnO layer, and separating the intermediate ZnO layer by wet etching with an etching liquid only for the ZnO layer.

Abstract: A method of fabricating flat-cell mask ROM devices having buried bit-lines that will not be subject to punch-through between neighboring bit lines as a result of heating in subsequent steps after the buried bit-lines are formed. In the method, the first step is to prepare a semiconductor substrate with a gate oxide layer formed thereon. Thereafter, a first polysilicon layer is formed over the gate oxide layer, and a plurality of trenches at predetermined positions, with these trenches extending through the gate oxide and first polysilicon layer and into the substrate to a predetermined depth. Then, trenches are filled with tungsten to form a plurality of source/drain regions. A second polysilicon layer is then formed over the first polysilicon layer, and an insulating layers is formed over each of the source/drain regions.

Abstract: A method of measuring a semiconductor device in forming a capacitor by successively laminating a dielectric film and an opposed electrode above an upper face of a charge storing electrode a surface of which is formed in an irregular shaper, including the steps of forming the irregular shape of the charge storing electrode and measuring an area of the charge storing electrode which is to constitute an effective area of the capacitor by an atomic force microscope.

Abstract: Undesirable counter doping of n.sup.+ /p.sup.+ gates illustratively through cross diffusion through an overlying silicide is inhibited by insertion of layers of titanium nitride and titanium, tungsten or tantalum between the polysilicon gates and an overlying silicide.

Abstract: A semiconductor device and method of manufacture thereof is provided. According to one embodiment, a semiconductor device is formed by forming a trench within a substrate. An oxide layer is formed within the trench and portions of the oxide layer are removed to expose one or more portions of the substrate within the trench. A plurality of doped polysilicon pillars are formed within the trench. The doped polysilicon pillars include one or more active region pillars formed on the one or more exposed portions of the substrate.

Abstract: A method for fabricating a multiple layer semiconductor device, such as a laser, using impurity-induced, or vacancy-enhanced, intermixing of semiconductor layers to selectively inactivate quantum well regions in the device.

Abstract: Methods of producing ferroelectric capacitors where the electrodes are formed in a contact hole. These methods include the steps of forming an insulating layer on an integrated circuit substrate. A contact hole is then formed through the insulating layer layer to expose a region of the integrated circuit substrate and to define a storage node pattern. A layer of oxidation-resistant conductive material is formed in the contact hole and the insulating layer removed to define a first storage electrode by exposing the layer of oxidation-resistant conductive material. A ferroelectric layer is then formed on the first storage electrode and a second storage electrode is formed on the ferroelectric layer opposite the first storage electrode.

Abstract: An improved p+ polysilicon gated PMOSFET having a channel on the surface of a silicon substrate and improved short channel behavior is disclosed. A simplified process allows making a p+ doped gate and source/drain regions at the same time, the transistor particularly having a stable threshold voltage. The disclosed method provides the steps of: (A) forming an active region and an insulation region on an n-type semiconductor substrate; growing a gate insulating layer on the silicon substrate; depositing a polysilicon layer on the gate insulating layer; annealing the polysilicon layer in the presence of NH.sub.3 or other nitrogen-containing gas; (C) forming a gate line by patterning and etching the polysilicon layer; and (D) implanting BF.sub.2 ions into the semiconductor substrate.

Abstract: A method for counteracting increases in resistivity encountered when Indium Oxide resistive layers are subjected to high temperature annealing steps during semiconductor device fabrication. The method utilizes a recovery annealing step which returns the Indium Oxide layer to its original resistivity after a high temperature annealing step has caused the resistivity to increase. The recovery anneal comprises heating the resistive layer to a temperature between 100.degree. C. and 300.degree. C. for a period of time that depends on the annealing temperature. The recovery is observed even when the Indium Oxide layer is sealed under a dielectric layer.

Abstract: Methods of forming thin-film transistors include the steps of forming an amorphous silicon (a-Si) layer of predetermined conductivity type on a face of an electrically insulating substrate and then forming a first insulating layer on the amorphous silicon layer. The first insulating layer and amorphous silicon layer are then patterned to define spaced amorphous source and drain regions having exposed sidewalls. An amorphous silicon channel region is then deposited in the space between the source and drain regions and in contact with the sidewalls thereof. An annealing step is then performed to convert the amorphous source, drain and channel regions to polycrystalline silicon, prior to the step of forming an insulated gate electrode on the channel region.

Abstract: A method for manufacturing a semiconductor device having a stacked gate electrode structure of self-aligned polysilicon-metal, which is capable of minimizing the variation in structural and electrical characteristics of the gate electrode, while utilizing the manufacturing process of forming a conventional silicone semiconductor memory device, is disclosed. According to the method for manufacturing a semiconductor device of the present invention, the conventional technique generally used in the manufacturing process of forming the silicon semiconductor device can be effectively utilized. Further, an excessive etch loss in the oxide layer can be restrained by using the oxide spacer of the self-aligned oxide layer in forming the metal layer at the gate electrode structure. Furthermore, it has an advantageous effect that the stable electrical characteristics of the resulting device can be obtained by using the polysilicon layer as a basic constituting material of the gate electrode thereof.

Abstract: A method for forming a ferroelectric material film, more particularly a lead zirconate titanate (PZT) film by the sol-gel method wherein a lowered oxidative sintering temperature may be adopted in preparing the ferroelectric material film with a perovskite crystalline structure, thereby reducing the risk of oxidation of metal electrodes and other circuits when the ferroelectric material film is employed as a dielectric in semiconductor devices, such as in a capacitor, for example. The method contemplates the preparation of a raw material solution containing an organometallic compound of a metallic element forming the ferroelectric material film, alkanolamine and/or stabilizer comprising a .beta.-diketone, with the concentration of the stabilizer being sufficient to provide a mole ratio to the total metal atoms of (stabilizer/total metal atoms)>3.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first metal film including a first metal on a surface of a silicon film by sputtering using a gas mixture added with a nitrogen gas, the first metal being one of nickel and cobalt, and causing thermal reaction of the silicon film with the first metal film to form a silicide film of the first metal.

Abstract: An object of the present invention is to completely reduce a difference in level in a short time at a convex pattern spreading horizontally on a large scale and obtain a semiconductor device having a planarized surface. An insulating film is formed on a semiconductor substrate to cover a horizontally spreading convex pattern and to fill in a concave portion. A portion of insulating film located on a planarized portion of convex pattern is selectively etched away so as to leave a frame-shaped insulating film having a width of 1-500 .mu.m at least on the outer periphery portion of convex pattern. Insulating film left on semiconductor substrate is etched by chemical/mechanical polishing method, thereby planarizing a surface of the semiconductor substrate.

Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposition of the nonconformal source material is stopped and a flowable insulating material, such as spin on glass, is coated on nonconformal insulating material to fill the remaining gaps. After etching the surfaces of the nonconformal and flowable insulating materials, another insulating layer is deposited and planarized to the desired overall thickness of the insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines.

Abstract: Disclosed is a method for fabricating a semiconductor device, especially suitable for a highly-integrated semiconductor device. In the method, a lower tungsten silicide film having an amorphous construction is formed on a poly silicon film on a gate oxide film formed on a semiconductor substrate. On the lower tungsten silicide film, an upper tungsten silicide film having a plurality of small grains between which gaps are defined. Thereafter, oxide films are formed on the crystallized grains by heat treatment under an oxygen atmosphere.

Abstract: A ferroelectric cell in which a ferroelectric stack of a perovskite ferroelectric sandwiched by cubic perovskite metal-oxide conductive electrodes are formed over a silicon body, such as a polysilicon plug penetrating a field oxide over a silicon transistor. According to the invention, an oxidation barrier is placed between the lower metal-oxide electrode and the polysilicon. The oxidation barrier may be: (1) a refractory metal sandwiched between two platinum layer which forms a refractory oxide in a platinum matrix; (2) an intermetallic barrier beneath a platinum electrode, e.g., of NiAl; or (3) a combination of Ru and SrRuO.sub.3 or similar materials. Thereby, the polysilicon plug is protected from oxidation.

Abstract: According to the present invention, a method for producing a semiconductor device in which an active region made of a crystalline silicon film is formed on an insulating surface of a substrate is provided.