Patents Examined by Cheung Lee
  • Semiconductor device and method for manufacturing the semiconductor device
    Patent number: 11600489
    Abstract: A semiconductor device having favorable electrical characteristics is provided. A metal oxide is formed over a substrate by the steps of: introducing a first precursor into a chamber in which the substrate is provided; introducing a first oxidizer after the introduction of the first precursor; introducing a second precursor after the introduction of the first oxidizer; and introducing a second oxidizer after the introduction of the second precursor.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 7, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tetsuya Kakehata, Yuji Egi, Yasuhiro Jinbo, Yujiro Sakurada
  • Thin film transistor and vertical non-volatile memory device including metal oxide channel layer having bixbyite crystal
    Patent number: 11588057
    Abstract: A thin film transistor and a non-volatile memory device are provided. The thin film transistor comprises a gate electrode, and a metal oxide channel layer traversing the upper or lower portions of the gate electrode. The metal oxide channel layer has semiconductor properties while having bixbyite crystals. An insulating layer is disposed between the gate electrode and the metal oxide channel layer. Source and drain electrodes are electrically connected to both ends of the metal oxide channel layer, respectively.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: February 21, 2023
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Jae Kyeong Jeong, Hyun Ji Yang, Hyeon Joo Seul
  • Memory cell device with thin-film transistor selector and methods for forming the same
    Patent number: 11581366
    Abstract: A memory structure, device, and method of making the same, the memory structure including a surrounding gate thin film transistor (TFT) and a memory cell stacked on the GAA transistor. The GAA transistor includes: a channel comprising a semiconductor material; a source electrode electrically connected to a first end of the channel; a drain electrode electrically connected to an opposing second end of the channel; a high-k dielectric layer surrounding the channel; and a gate electrode surrounding the high-k dielectric layer. The memory cell includes a first electrode that is electrically connected to the drain electrode.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yong-Jie Wu, Yen-Chung Ho, Hui-Hsien Wei, Chia-Jung Yu, Pin-Cheng Hsu, Mauricio Manfrini, Chung-Te Lin
  • Van der Waals integration approach for material integration and device fabrication
    Patent number: 11575006
    Abstract: An electronic or optoelectronic device includes: (1) a layer of a first material; and (2) a layer of a second material disposed on the layer of the first material, wherein the first material is different from the second material, and the layer of the first material is spaced from the layer of the second material by a gap.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 7, 2023
    Assignee: The Regents of the University of California
    Inventors: Xiangfeng Duan, Yu Huang, Yuan Liu
  • Thin film transistor and display apparatus comprising the same
    Patent number: 11574843
    Abstract: Disclosed is a thin film transistor, a method for manufacturing the same and a display apparatus comprising the same, wherein the thin film transistor includes a first insulating layer on a substrate, an active layer on the first insulating layer, and a gate electrode spaced apart from the active layer and configured to have at least a portion overlapped with the active layer, wherein the active layer has a single crystal structure of an oxide semiconductor material, and an upper surface of the first insulating layer which contacts the active layer is an oxygen (O) layer made of oxygen (O).
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: February 7, 2023
    Assignee: LG Display Co., Ltd.
    Inventors: KyungChul Ok, JungSeok Seo, PilSang Yun, Jiyong Noh, Jaeman Jang, InTak Cho
  • Vertical heterostructure semiconductor memory cell and methods for making the same
    Patent number: 11569244
    Abstract: A memory cell comprises a nanowire structure comprising a channel region and source/drain regions of a transistor. The nanowire structure also comprises as first conductor of a capacitive device as a vertical extension of the nanowire structure.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Gerben Doornbos, Marcus Johannes Henricus Van Dal
  • 3D stackable bidirectional access device for memory array
    Patent number: 11562931
    Abstract: A method of manufacturing a vertical metal-semiconductor field-effect transistor (MESFET) device is provided. The method includes forming a first oxide layer, forming a first electrode in the oxide layer, forming a crystallized silicon layer on the first electrode, forming a second electrode on the first oxide layer and on sidewalls of the crystalized silicon layer, forming a second oxide layer on upper surfaces of the second electrode. The method also includes forming a third electrode on an upper surface of the crystallized silicon layer.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: January 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: Fabio Carta, Matthew Joseph BrightSky
  • Multilayer diamond display system and method
    Patent number: 11552276
    Abstract: Disclosed herein is a transparent glass system that includes an optical grade silicon substrate, a transparent substrate layer; a titanium dioxide transparent layer, the transparent layer having an index of refraction of 2.35 or greater; and a polycrystalline diamond layer, wherein the transparent layer is between the substrate layer and the polycrystalline diamond layer.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: January 10, 2023
    Assignee: AKHAN Semiconductor, Inc.
    Inventors: Adam Khan, Robert Polak, Priya Raman
  • Formation of a Ga-doped SiGe and B/Ga-doped SiGe layers
    Patent number: 11545357
    Abstract: A method for forming a Ga-doped SiGe layer comprises depositing, in the presence of a C-containing Ga precursor, Ga-doped SiGe on a substrate, thereby forming a first portion of the Ga-doped SiGe layer. The method further comprises depositing, in the absence of the C-containing Ga precursor, SiGe on the first portion, thereby forming a second portion of the Ga-doped SiGe layer.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: January 3, 2023
    Assignee: IMEC VZW
    Inventors: Andriy Hikavyy, Clement Porret
  • Semiconductor device and method
    Patent number: 11545559
    Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yoh-Rong Liu, Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu, Li-Chi Yu, Sen-Hong Syue
  • Spacer structure for semiconductor device and method for forming the same
    Patent number: 11545397
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: January 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Yu Lin, Jhih-Rong Huang, Yen-Tien Tung, Tzer-Min Shen, Fu-Ting Yen, Gary Chan, Keng-Chu Lin, Li-Te Lin, Pinyen Lin
  • Nanostructures and method for manufacturing the same
    Patent number: 11538927
    Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes forming a stack of a first type and a second type epitaxial layers on a frontside of a semiconductor substrate, patterning the stack to form a fin-shaped structure, depositing a dielectric layer on sidewalls of the fin-shaped structure, and recessing the dielectric layer to expose a top portion of the fin-shaped structure. A top surface of the recessed dielectric layer is above a bottom surface of the stack. The exemplary manufacturing method also includes forming a gate structure over the top portion of the fin-shaped structure, etching the semiconductor substrate from a backside of the semiconductor substrate, and etching at least a bottommost first type epitaxial layer and a bottommost second type epitaxial layer through the trench.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: December 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Chiang, Yen-Ming Chen, Jung-Chien Cheng, Chih-Hao Wang, Kuan-Lun Cheng
  • 3D cross-bar nonvolatile memory
    Patent number: 11532705
    Abstract: Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz, Ta-Pen Guo
  • Method for forming sidewall spacers and semiconductor devices fabricated thereof
    Patent number: 11532725
    Abstract: Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Ting Pan, Kuo-Cheng Chiang, Shi Ning Ju, Yi-Ruei Jhan, Kuan-Lun Cheng, Chih-Hao Wang
  • Non-volatile memory device with reduced area
    Patent number: 11532752
    Abstract: A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, and a first gate electrode and a second gate electrode over the substrate and extending in a second direction. The semiconductor fin extends through the second gate electrode and terminates on the first gate electrode at one end. The memory device further includes a first conductive via over and electrically coupled to the first gate electrode. The one end of the semiconductor fin is surrounded by the first gate electrode.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yao-Jen Yang, Yih Wang
  • Multi-gate device and method of fabrication thereof
    Patent number: 11532732
    Abstract: A method includes forming a semiconductor fin extruding from a substrate; forming a sacrificial capping layer on sidewalls of the semiconductor fin; forming first and second dielectric fins sandwiching the semiconductor fin; forming a sacrificial gate stack over the semiconductor fin, the sacrificial capping layer, and the first and second dielectric fins; forming gate spacers on sidewalls of the sacrificial gate stack; removing the sacrificial gate stack to form a gate trench, wherein the gate trench exposes the semiconductor fin, the sacrificial capping layer, and the first and second dielectric fins; removing the sacrificial capping layer from the gate trench, thereby exposing the sidewalls of the semiconductor fin; and forming a metal gate stack in the gate trench engaging the semiconductor fin.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Ruei Jhan, Kuan-Ting Pan, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Semiconductor device
    Patent number: 11532736
    Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: December 20, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Daisuke Tokuda, Tsunekazu Saimei, Hiroaki Tokuya
  • Method of manufacturing a semiconductor device and a semiconductor device
    Patent number: 11508621
    Abstract: A semiconductor device includes semiconductor nanostructures disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor nanostructures, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor nanostructures, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor nanostructures, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Shahaji B. More
  • Hybrid ultrasonic transducer and method of forming the same
    Patent number: 11508902
    Abstract: A method of manufacturing a semiconductor device includes: forming a first substrate includes a membrane stack over a first dielectric layer, the membrane stack having a first electrode, a second electrode over the first electrode and a piezoelectric layer between the first electrode and the second electrode, a third electrode over the first dielectric layer, and a second dielectric layer over the membrane stack and the third electrode; forming a second substrate, including: a redistribution layer (RDL) over a third substrate, the RDL having a fourth electrode; and a first cavity on a surface of the RDL adjacent to the fourth electrode; forming a second cavity in one of the first substrate and the second substrate; and bonding the first substrate to the second substrate.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi Heng Tsai, Fu-Chun Huang, Ching-Hui Lin, Chun-Ren Cheng
  • Manufacturing method of semiconductor device
    Patent number: 11508850
    Abstract: A manufacturing method of a semiconductor device includes the forming a first oxide over a substrate; depositing a first insulator over the first oxide; forming an opening reaching the first oxide in the first insulator; depositing a first oxide film in contact with the first oxide and the first insulator in the opening; depositing a first insulating film over the first oxide film by a PEALD method; depositing a first conductive film over the first insulating film; and removing part of the first oxide film, part of the first insulating film, and part of the first conductive film until a top surface of the first insulator is exposed to form a second oxide, a second insulator, and a first conductor. The deposition of the first insulating film is performed while the substrate is heated to higher than or equal to 300°.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 22, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Naoki Okuno, Tetsuya Kakehata, Hiroki Komagata, Yuji Egi