Patents Examined by Choung A Luu
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Patent number: 9153528Abstract: Embodiments of the present invention provide a chip package including: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface; and a conducting pad structure disposed in the dielectric layer and electrically connected to the device region; a cover substrate disposed between the chip and the cover substrate, wherein the spacer layer, a cavity is created an surrounded by the chip and the cover substrate on the device region, and the spacer layer is in direct contact with the chip without any adhesion glue disposed between the chip and the spacer layer.Type: GrantFiled: May 20, 2013Date of Patent: October 6, 2015Assignee: XINTEC INC.Inventors: Po-Shen Lin, Tsang-Yu Liu, Yen-Shih Ho, Chih-Wei Ho, Yu-Min Liang
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Patent number: 9023694Abstract: A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of a conductivity type opposite to the body region of the semiconductor fin. A metal semiconductor alloy portion is formed directly on the two source regions and the top surface of the exposed body region between the two source regions. The doping concentration of the exposed top portion of the body region may be increased by ion implantation to provide a low-resistance contact to the body region, or a recombination region having a high-density of crystalline defects may be formed. A hybrid surface semiconductor-on-insulator (HSSOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) thus formed has a body region that is electrically tied to the source region.Type: GrantFiled: February 22, 2013Date of Patent: May 5, 2015Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Patent number: 8900897Abstract: Devices are described including a component comprising an alloy of AlN and AlSb. The component has an index of refraction substantially the same as that of a semiconductor in the optoelectronic device, and has high transparency at wavelengths of light used in the optoelectronic device. The component is in contact with the semiconductor in the optoelectronic device. The alloy comprises between 0% and 100% AlN by weight and between 0% and 100% AlSb by weight. The semiconductor can be a III-V semiconductor such as GaAs or AlGaInP. The component can be used as a transparent insulator. The alloy can also be doped to form either a p-type conductor or an n-type conductor, and the component can be used as a transparent conductor. Methods of making and devices utilizing the alloy are also disclosed.Type: GrantFiled: January 10, 2013Date of Patent: December 2, 2014Assignee: Intermolecular, Inc.Inventors: Philip Kraus, Thai Cheng Chua, Yoga Saripalli
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Patent number: 8624323Abstract: A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate.Type: GrantFiled: May 31, 2011Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: Stephen M. Gates, Daniel C. Edelstein, Satyanarayana V. Nitta
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Patent number: 8580631Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.Type: GrantFiled: October 21, 2011Date of Patent: November 12, 2013Assignee: Texas Instruments IncorporatedInventors: Rajni J. Aggarwal, Jau-Yuann Yang
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Patent number: 8372750Abstract: According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.Type: GrantFiled: September 24, 2010Date of Patent: February 12, 2013Assignee: Texas Instruments IncorporatedInventors: Amitabh Jain, Peijun Chen, Jorge A. Kittl
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Patent number: 7863114Abstract: The present invention provides a method for removing a metal element effectively from a crystalline semiconductor film obtained with the use of the metal element, without increasing the number of processes. In the present invention, an amorphous semiconductor film is formed on an insulating surface, a metal element for promoting crystallization is added to the amorphous semiconductor film, the amorphous semiconductor film is heated to form a crystallized semiconductor film, a continuous wave laser beam is irradiated to the crystallized semiconductor film, and an upper portion of the crystallized semiconductor film is removed.Type: GrantFiled: January 8, 2008Date of Patent: January 4, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinji Maekawa, Hidekazu Miyairi
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Patent number: 6531365Abstract: A method for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided.Type: GrantFiled: June 22, 2001Date of Patent: March 11, 2003Assignee: International Business Machines CorporationInventors: Omer H. Dokumaci, Bruce B. Doris, Peter Smeys, Isabel Y. Yang