Abstract: A semiconductor device with high reliability, low voltage, and high luminance is provided by preventing detachment of an electrode by way of obtaining good adhesion of the electrode, even in cases where a face-down mounting of a semiconductor laser is performed, and further, an insulating film and a protective film etc. are disposed in the area other than the area where the electrode is ohmically connected to the semiconductor layer. In a semiconductor device having an electrode electrically connected to the semiconductor layer, a dielectric film and an adhesion film comprising a degenerate semiconductor are stacked in sequence on a portion of a region between the semiconductor layer and the electrode, and the adhesion film is in contact with the electrode.

Abstract: A semiconductor chip comprises a silicon substrate on which semiconductor elements are formed, pads, each of which is formed on the silicon substrate and electrically connected to at least one of the semiconductor elements, a first insulating layer having an opening over each one of the pads, a first wiring layer formed on the first insulating layer, electrically connected to the pads and having connecting parts, a second insulating layer formed on the first wiring layer and having openings over the connecting parts of the first wiring layer, electrically functioning solder bumps, each of which is formed on one of the openings of the second insulating layer with electrically connecting to one of the pads via the first wiring layer, and dummy bumps for self adjustment, each of which is formed on one of the openings of the second insulating layer without electrically connecting to the pad.

Abstract: A semiconductor device having a semiconductor chip stack on a rewiring plate is disclosed. In one embodiment, the device includes an external contact area having a plurality of external contact area regions which are physically separate from one another is arranged on the underside. The individual external contact area regions are assigned to the individual semiconductor chips in the semiconductor chip stack. The external contact regions of an individual external contact area have a common external contact which electrically connects the external contact area regions.

Abstract: The present invention provides a resin-encapsulated semiconductor apparatus comprising a semiconductor device having a ferroelectric film and a surface-protective film, and an encapsulant member comprising a resin; the surface-protective film being formed of a polyimide. The present invention also provides a process for fabricating a resin-encapsulated semiconductor apparatus, comprising the steps of forming a film of a polyimide precursor composition on the surface of a semiconductor device having a ferroelectric film; heat-curing the polyimide precursor composition film to form a surface-protective film formed of a polyimide; and encapsulating, with an encapsulant resin, the semiconductor device on which the surface-protective film has been formed. The polyimide may preferably have a glass transition temperature of from 240° C. to 400° C. and a Young's modulus of from 2,600 MPa to 6 GPa. The curing may preferably be carried out at a temperature of from 230° C. to 300° C.

Abstract: A stacked electronics module comprises a first layer including a first substrate having a front side and a backside, a first electrical interconnect layer disposed on the first substrate and a first electronic device disposed on the front side of the first substrate. In addition, the stacked electronics module comprises a second layer including a second substrate having a front side and a backside, a second electrical interconnect layer disposed on the second substrate and a second electronic device disposed on the front side of the second substrate.

Abstract: This embodiment addresses a novel Chip-to-wafer chip lamination technique that provides low cost and high throughput. In the Chip-to-Chip process, using the temperature rise and utilizing deformation caused by thermal expansion of a metal shim inserted between the inner wall of a cavity, in which multiple chips are laminated and accommodated, multiple chips in the cavity are pressed against a reference surface on a side wall of the cavity to automatically perform positioning.

Abstract: A multiple die package for integrated circuits is disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one lead of a first leadframe overlying one surface of the insulator layer. At least one second integrated circuit is provided and electrically coupled to a second leadframe overlying a second surface of the insulator layer. Electrical connections between the two leadframes and the first and second integrated circuits are made through the insulator, at selected locations, by coupling at least one lead of the first and second leadframes one to another. The leads of the first and second leadframe may be physically coupled by a welding process within vias in the insulator. A removable storage card package is also described.

Abstract: In a pressing cap forming part of a semiconductor device carrier unit, a pressing portion of a pressure body has recesses, to each of which a bump is inserted.

Abstract: In a semiconductor device having a WCSP type construction package, to increase inductance without increasing further an area conventionally occupied by a coil. A pseudo-post part 27 comprising a magnetic body is extended in a direction perpendicular to a main surface 12a of a semiconductor chip 12, on a second insulating layer 21 of a WCSP 10. A first conductive part 15a and a second conductive part 15b constructed as square frames are respectively provided so as to surround the pseudo-post part, on respective top surfaces of a second insulation layer and a third insulating layer 22 which are separated parallel to each other, in an extension direction of the pseudo-post part. A coil 100 being a substantially spiral shape conductive path is formed from, the first conductive part, the second conductive part, and a connection part 26 which electrically connects the one ends of the first and second conductive parts.

Abstract: A surface mount electronic chip (10) is mounted on a holder (70) and electrically connected to holder terminals (74,76, 80) by the use of a carrier device (30). The carrier device has clips (36) mounted on walls of the carrier frame. The chip is merely pressed into a cavity (48) between inner tabs (44) of the chips. The carrier with the chip in place is merely pressed into a cradle (78) formed in the holder by the holder terminals, so outer tabs (46) of the clips press against the holder terminals.

Abstract: First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Next, an amorphous silicon layer is deposited, an annealing process is executed to form inter-layer reaction layers on the drain electrode, the gate pa and the data pad, which are exposed through the contact holes. Then, the amorphous silicon layer is removed.

Abstract: A leadframe with a structure made of a base metal (105), wherein the structure has a plurality of surfaces. On each of these surfaces are metal layers in a stack adherent to the base metal. The stack comprises a nickel layer (201) in contact with the base metal, a palladium layer (202) in contact with the nickel layer, and an outermost tin layer (203) in contact with the palladium layer. In terms of preferred layer thicknesses, the nickel layer is between about 0.5 and 2.0 ?m thick, the palladium layer between about 5 and 150 nm thick, and the tin layer less than about 5 nm thick, preferably about 3 nm. At this thinness, the tin has no capability of forming whiskers, but offers superb adhesion to polymeric encapsulation materials, improved characteristics for reliable stitch bonding as well as affinity to reflow metals (solders).

Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.

Abstract: A heat dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted on a chip carrier. A heat sink is mounted on the chip, and includes an insulating core layer, a thin metallic layer formed on each of an upper surface and a lower surface of the insulating core layer and a thermal via hole formed in the insulating core layer. A molding process is performed to encapsulate the chip and the heat sink with an encapsulant to form a package unit. A singulation process is performed to peripherally cut the package unit. A part of the encapsulant above the thin metallic layer on the upper surface of the heat sink is removed, such that the thin metallic layer on the upper surface of the heat sink is exposed, and heat generated by the chip can be dissipated through the heat sink.

Abstract: A semiconductor device comprises: a semiconductor chip; a first frame; a solder layer which bonds the solder bonding metal layer of the semiconductor chip and the first frame; and a second frame bonded to the rear face of the semiconductor chip. The semiconductor chip includes: a semiconductor substrate; a first metal layer provided on a major surface of the semiconductor substrate and forming a Schottky junction with the semiconductor substrate; a second metal layer provided on the first metal layer and primarily composed of aluminum; a third metal layer provided on the second metal layer and primarily composed of molybdenum or titanium; and a solder bonding metal layer provided on the third metal layer and including at least a fourth metal layer which is primarily composed of nickel, ion or cobalt.

Abstract: Disclosed herein is a device package that comprises a device having a top substrate that is disposed on a supporting surface of a package substrate. A package frame contacts the top surface of the top substrate and top surface of the package substrate, and hermetically seals the device between the top surfaces of the top substrate and package substrate. The device can be a semiconductor device, a microstructure such as a microelectromechanical device, or other devices.

Abstract: In a wafer (1) with a number of exposure fields (2), each of which exposure fields (2) comprises a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of dicing paths (6, 8) are provided and two control module fields (A1, A2, B1, B2, C1, D1, D2, E1, E2, F1) are assigned to each exposure field (2), each of which control module fields extends parallel to a first direction (X) and contains at least one optical control module (OCM-A1, OCM-A2, OCM-BI, OCM-B2, OCM-C1, OCM-D1, OCM-D2, OCM-E1, OCME2, OCM-F1), wherein a first control module field (OCM-A1, OCM-B1, OCM-C1, OCMD1, OCM-E1, OCM-F1) of each exposure field (2) is located between a first edge (R1, S1, T1, U1, V1, Z1) and a row of lattice fields (3) of the exposure field (2) in question and a second control module field (OCM-A2, OCM-B2, OCM-D2, OCM-E2) is located between two rows of lattice fields (3) of the exposure field (2) in question, which are arranged adjacent to a second edge (R2, S1, U2, V2), and wherein both the first contr

Abstract: Means for forming a package is disclosed on which is mounted a semiconductor chip with a high-speed LSI formed thereon, using a wire bonding method. The package comprises a semiconductor chip, a die pad smaller than a main surface of the semiconductor chip, a sealing member, plural leads each comprising an outer terminal portion and an inner lead portion, and plural bonding wires for connection between bonding pads formed on the semiconductor chip and the inner lead portions of the leads, each of the inner lead portions being bent in a direction away from a mounting surface of the sealing member, thereby approximating the height of the chip-side bonding pads and that of a bonding position of the inner lead portions to each other, whereby the wire length can be made shorter and it is possible to suppress an increase in inductance of the wire portions and attain impedance matching at various portion of a high-frequency signal input/output transmission path.

Abstract: A chip package with asymmetric molding including a lead frame, a chip, an adhesive layer, bonding wires and an encapsulant, is provided. The lead frame includes a frame body and at least a turbulent plate. The frame body has inner lead portions and outer lead portions. The turbulent plate is bended upwards to form a bulge portion and the first end of the turbulent plate is connected to the frame body. The chip is fixed under the inner lead portions and the turbulent plate is located at one side of the chip. The adhesive layer is disposed between the chip and the inner lead portions, and the bonding wires are electrically connected between the chip and the corresponding inner lead portions, respectively. The encapsulant encapsulates at least the chip, the bonding wires, the inner lead portions, the adhesive layer and the turbulent plate.

Abstract: Provided are a semiconductor lead frame, a semiconductor package having the semiconductor lead frame, and a method of plating the semiconductor lead frame. The method includes preparing a substrate formed of a Fe—Ni alloy (alloy 42), and a plating layer that contains grains less than 1 micrometer in size and is plated on the substrate. The growth of whiskers when a Sn plated layer is formed on a substrate formed of a Fe—Ni alloy (alloy 42) can be suppressed by minimizing the grain size of the Sn plated layer.