Abstract: A display panel has a display region and at least one bonding region located beside the display region. The display panel includes: a base; and a plurality of conductive pads provided on the base and located in each bonding region. The plurality of conductive pads are arranged at intervals along a first direction. The plurality of conductive pads include at least one first type of conductive pad configured to transmit a direct current voltage signal to the display region and a plurality of second type of conductive pads configured to transmit a pulse voltage signal to the display region. A dimension of one first type of conductive pad in the first direction is greater than a dimension of one second type of conductive pad in the first direction.

Abstract: Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.

Abstract: A package structure including a first die, a second die, a dielectric body, a conductive terminal, a circuit layer and a patterned insulating layer is provided. The second die is disposed on the first die. A second active surface of the second die faces a first active surface of the first die. The dielectric body covers the first die. The conductive terminal is disposed on the dielectric body and opposite to the second die. The circuit layer includes a first circuit portion and a second circuit portion. The first circuit portion penetrates the dielectric body. The first die is electrically connected to the conductive terminal through the first circuit portion. The second circuit portion is embedded in the dielectric body. The second die is electrically connected to the first die through the second circuit portion. The patterned insulating layer covers the circuit layer and is embedded in the dielectric body.

Abstract: A method for fabricating packaged semiconductor devices is disclosed. In one example the method comprises providing a plurality of semiconductor dies, the semiconductor dies being arranged in an array on a carrier such that a first side of the semiconductor dies faces the carrier and such that an empty space is arranged laterally besides each semiconductor die. A substrate comprising a plurality of conductive elements is arranged over the plurality of semiconductor dies such that a conductive element is arranged in the respective empty space besides each one of the semiconductor dies. The plurality of semiconductor dies are molded over to form a molded body, and singulating packaged semiconductor devices from the molded body by cutting through the molded body.

Abstract: A package structure includes a first die, a second die over and electrically connected to the first die, an insulating material around the second die, a first antenna extending through the insulating material and electrically connected to the second die, the first antenna being adjacent to a first sidewall of the second die, wherein the first antenna includes a first conductive plate extending through the insulating material, and a plurality of first conductive pillars extending through the insulating material, wherein the first conductive plate is between the plurality of first conductive pillars and the first sidewall of the second die.

Abstract: Discussed are a lamp or a lamp device employing a semiconductor light-emitting element to have a high degree of luminance uniformity. A lamp includes a circuit board; a bus electrode formed along one direction on the circuit board; electrode lines on the circuit board to extend from the bus electrode; semiconductor light-emitting elements arranged in the direction in which the electrode lines are formed, and spaced a predetermined distance apart from a nearby electrode line; transparent electrodes for electrically connecting the semiconductor light-emitting elements to the electrode lines; a current input unit formed along the one direction in parallel to the bus electrode; and connecting electrodes arranged between the bus electrode and the current input unit along the one direction, to electrically connect the bus electrode to the current input unit, wherein a resistance value of certain of the connecting electrodes is different from a resistance value of the rest.

Abstract: A semiconductor device has a substrate and a first light sensitive material formed over the substrate. A plurality of first conductive posts is formed over the substrate by patterning the first light sensitive material and filling the pattern with a conductive material. A plurality of electrical contacts is formed over the substrate and the conductive posts are formed over the electrical contacts. A first electric component is disposed over the substrate between the first conductive posts. A plurality of second conductive posts is formed over the first electrical component by patterning a second light sensitive material and filling the pattern with conductive material. A first encapsulant is deposited over the first electrical component and conductive posts. A portion of the first encapsulant is removed to expose the first conductive posts. A second electrical component is disposed over the first electrical component and covered with a second encapsulant.

Abstract: A package includes a redistribution structure, a die package on a first side of the redistribution structure including a first die connected to a second die by metal-to-metal bonding and dielectric-to-dielectric bonding, a dielectric material over the first die and the second die and surrounding the first die, and a first through via extending through the dielectric material and connected to the first die and a first via of the redistribution structure, a semiconductor device on the first side of the redistribution structure includes a conductive connector, wherein a second via of the redistribution structure contacts the conductive connector of the semiconductor device, a first molding material on the redistribution structure and surrounding the die package and the semiconductor device, and a package through via extending through the first molding material to contact a third via of the redistribution structure.

Abstract: A mold structure includes gate electrodes stacked on a first substrate, a channel structure penetrating a first region of the mold structure to cross the gate electrodes, a first through structure penetrating a second region of the mold structure, and a second through structure penetrating a third region of the mold structure. The mold structure includes memory cell blocks extending in a first direction and spaced apart in a second direction, and a dummy block extending in the first direction and disposed between the memory cell blocks. Each of the memory cell and dummy blocks includes a cell region and an extension region arranged in the first direction. The first region is the cell region of one of the memory cell blocks, the second region is the extension region of the one of the memory cell blocks, and the third region is the extension region of the dummy block.

Abstract: Some features pertain to a hybrid package that includes a die, a first substrate structure, and a first metallization structure that is at least partially coplanar with the substrate. The die is electrically coupled to the first metallization structure and the first substrate through a second metallization structure. The first metallization structure is configured to provide an electrical path for data signaling. The second metallization structure is configured as a ground plane and is coupled to a ground signal. The first substrate structure is configured to provide an electrical path for power signaling.

Abstract: A deposition mask group includes a first deposition mask having two or more first through holes arranged along two different directions, a second deposition mask having two or more second through holes arranged along two different directions and a third deposition mask having two or more third through holes. The first through hole and the second through hole or the third through hole partly overlap when the first deposition mask, the second deposition mask and the third deposition mask are overlapped.

Abstract: In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.

Abstract: A semiconductor package is disclosed. The semiconductor package includes a back-side wiring substrate and a front-side redistribution layer which are in parallel, and a connector, a semiconductor chip and an encapsulator which are between the back-side wiring substrate and the front-side redistribution layer. The encapsulator surrounds surfaces of the connector and the semiconductor chip. The back-side wiring substrate includes a core layer, a back-side via plug extending through the core layer, and a back-side redistribution layer on the back-side via plug.

Abstract: A semiconductor package includes a front redistribution structure having a first surface and a second surface, opposite to the first surface, a dielectric layer, an antenna substrate including a plurality of antenna members in the dielectric layer, a semiconductor chip having a connection pad connected to the plurality of antenna members, a conductive core structure having a first through-hole accommodating the antenna substrate and a second through-hole accommodating the semiconductor chip, and a rear redistribution structure including a conductive cover layer exposing an upper portion of the antenna substrate and covering an upper portion of the semiconductor chip, and a conductive via connecting the conductive cover layer to the conductive core structure.

Abstract: A structure includes a redistribution structure, which includes a bottom layer and a plurality of upper layers over the bottom layer. The redistribution structure also includes a power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers, and a metal pad in the bottom layer and overlapped by the power-ground macro. The metal pad is electrically disconnected from the power-ground macro.

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.

Abstract: Embodiments disclosed herein are directed to forming MOSFET devices. In particular, one or more pre-silicide treatments are performed on a substrate prior to the deposition of the metal-silicide layer to improve the density and performance of the metal-silicide layer in the MOSFETs. The metal-silicide formation formed with the pre-silicide treatment(s) can occur before or after the formation of metal gates during MOSFET fabrication.

Abstract: A semiconductor package includes a frame structure having a core portion and a lower pad under the core portion. A cavity penetrates the core portion, and a semiconductor chip is arranged in the cavity and has an active surface on which a bump pad is arranged and a non-active surface facing the active surface. A redistribution structure is positioned under the frame structure and the semiconductor chip, and is connected to the lower pad and the bump pad. A molding member covers the frame structure and the semiconductor chip and fills the cavity. The molding member surrounds a lower surface of the frame structure, the active surface of the semiconductor chip, the lower pad, and the bump pad.

Abstract: In-package radio frequency (RF) waveguides as high bandwidth chip-to-chip interconnects and methods for using the same are disclosed. In one example, an electronic package includes a package substrate, first and second silicon dies or tiles, and an RF waveguide. The first and second silicon dies or tiles are attached to the package substrate. The RF waveguide is formed in the package substrate and interconnects the first silicon die or tile with the second silicon die or tile.

Abstract: An optoelectronic device package includes a first redistribution layer (RDL), a first electronic die disposed over the first RDL, wherein an active surface of the first electronic die faces the first RDL. The optoelectronic device package further includes a second electronic die disposed over the first RDL, and a photonic die disposed over and electrically connected to the second electronic die. An active surface of the second electronic die is opposite to the first RDL.