Abstract: A structure includes a redistribution structure, which includes a bottom layer and a plurality of upper layers over the bottom layer. The redistribution structure also includes a power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers, and a metal pad in the bottom layer and overlapped by the power-ground macro. The metal pad is electrically disconnected from the power-ground macro.

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.

Abstract: Embodiments disclosed herein are directed to forming MOSFET devices. In particular, one or more pre-silicide treatments are performed on a substrate prior to the deposition of the metal-silicide layer to improve the density and performance of the metal-silicide layer in the MOSFETs. The metal-silicide formation formed with the pre-silicide treatment(s) can occur before or after the formation of metal gates during MOSFET fabrication.

Abstract: A semiconductor package includes a frame structure having a core portion and a lower pad under the core portion. A cavity penetrates the core portion, and a semiconductor chip is arranged in the cavity and has an active surface on which a bump pad is arranged and a non-active surface facing the active surface. A redistribution structure is positioned under the frame structure and the semiconductor chip, and is connected to the lower pad and the bump pad. A molding member covers the frame structure and the semiconductor chip and fills the cavity. The molding member surrounds a lower surface of the frame structure, the active surface of the semiconductor chip, the lower pad, and the bump pad.

Abstract: In-package radio frequency (RF) waveguides as high bandwidth chip-to-chip interconnects and methods for using the same are disclosed. In one example, an electronic package includes a package substrate, first and second silicon dies or tiles, and an RF waveguide. The first and second silicon dies or tiles are attached to the package substrate. The RF waveguide is formed in the package substrate and interconnects the first silicon die or tile with the second silicon die or tile.

Abstract: An optoelectronic device package includes a first redistribution layer (RDL), a first electronic die disposed over the first RDL, wherein an active surface of the first electronic die faces the first RDL. The optoelectronic device package further includes a second electronic die disposed over the first RDL, and a photonic die disposed over and electrically connected to the second electronic die. An active surface of the second electronic die is opposite to the first RDL.

Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

Abstract: A semiconductor package includes: a redistribution substrate including a connection via and a redistribution layer electrically connected to each other, and a redistribution pad electrically connected to the redistribution layer by the connection via, a space pattern separating at least some of the redistribution pads from each other, a dummy metal pattern at least partially surrounded by the space pattern, and a degassing opening passing through at least one of the redistribution pad and the dummy metal pattern; a connection bump electrically connected to the redistribution pad; and a semiconductor chip on the redistribution substrate and including a connection pad electrically connected to the redistribution layer, the redistribution pad including a plurality of protrusions protruding from the same plane in directions different from each other and having a corner having a rounded shape, and the dummy metal pattern includes branch patterns each extending in directions different from one another.

Abstract: A display apparatus includes a base substrate, a polysilicon active pattern disposed on the base substrate, including polycrystalline silicon, including a source region and a drain region each doped with impurities and a channel region between the source region and the drain region, and including indium, a first gate electrode overlapping the channel region, and a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region.

Abstract: A display panel includes an upper substrate to which external light is incident, a sealing member which is in a non-display area and couples the upper substrate to a lower display substrate. The upper display substrate includes: a base substrate; a light shielding layer and filter layer each corresponding to the non-display area and absorbing a portion of external light which is transmitted through the base substrate at the non-display area, the filter layer and the light shielding layer having different colors from each other. In a first non-display area of the base substrate which corresponds to the sealing member, only one among the filter layer and the light shielding layer is disposed. In a second non-display area of the base substrate which is adjacent to the first non-display area, both the filter layer and the light shielding layer are disposed.

Abstract: An electronic modulating device is provided. The electronic modulating device includes a first modulating unit. The first modulating unit includes a first transistor including a channel arranged in an extending direction. The first modulating unit also includes a first modulating electrode electrically connected to the first transistor and arranged in a first longitudinal direction. The electronic modulating device also includes a second modulating unit. The second modulating unit includes a second transistor including a channel arranged in the extending direction. The second modulating unit also includes a second modulating electrode electrically connected to the second transistor and arranged in a second longitudinal direction that is different from the first longitudinal direction. The first included angle between the extending direction and the first longitudinal direction is different from a second included angle between the extending direction and the second longitudinal direction.

Abstract: An improved memory module and methods for constructing the same are disclosed herein. The memory module includes a substrate having a first surface and a second surface opposite the first surface, each having a central portion, a first array area and a second array area. The first array area is cooler than the second array area during operation. The memory module also includes a power management integrated circuit attached to the central portion of the first surface. The memory module also includes a first semiconductor die attached to the substrate in the first array area. The first semiconductor die has a first performance rating of an operating parameter at high temperatures. The memory module also includes a second semiconductor die attached to the substrate in the second array area. The second semiconductor die has a second performance rating of an operating parameter better than the first performance rating at high temperatures.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a first fin, and the first fin has a channel region and a source/drain region. The method includes forming a stack structure over the first fin, and the stack structure includes a first semiconductor layer and a second semiconductor layer vertically stacked over the fin. The method also includes removing a portion of the second semiconductor layer in the channel region, and a portion of the first semiconductor layer is remaining in the channel region. The method further includes forming a cladding layer over the remaining first semiconductor material layer in the channel region to form a nanostructure, wherein the nanostructure has a dumbbell shape. The method includes forming a gate structure surrounding the nanostructure.

Abstract: A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.

Abstract: A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A display apparatus including a first non-folding area, a second non-folding area spaced apart from the first non-folding area, and a folding area between the first non-folding area and the second non-folding area, a flexible display panel, a metal plate supporting the flexible display panel and including a recess in the folding area, the metal plate having a first thickness in the first non-folding area and the second non-folding area, and a second thickness less than the first thickness in the folding area, a resin portion disposed in the recess, and a first adhesive layer disposed between the flexible display panel and the metal plate.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming an assembly including placing a semiconductor die and a launcher structure on a carrier substrate, encapsulating at least a portion of the semiconductor die and the launcher structure, and applying a redistribution layer on a surface of the semiconductor die and a surface of the launcher structure to connect a bond pad of the semiconductor die with an antenna launcher of the launcher structure. The assembly is attached to a substrate and a waveguide overlapping the assembly is attached to the substrate. The waveguide structure is physically decoupled from the assembly.

Abstract: Semiconductor devices and methods of manufacture are provided, in which an adhesive is removed from a semiconductor die embedded within an encapsulant, and an interface material is utilized to remove heat from the semiconductor device. The removal of the adhesive leaves behind a recess adjacent to a sidewall of the semiconductor, and the recess is filled.

Abstract: A method for processing a crystalline substrate to form multiple patterns of subsurface laser damage facilitates subsequent fracture of the substrate to yield first and second substrate portions of reduced thickness. Multiple (e.g., two, three, or more) groups of parallel lines of multiple subsurface laser damage patterns may be sequentially interspersed with one another, with at least some lines of different groups not crossing one another. Certain implementations include formation of multiple subsurface laser damage patterns including groups of parallel lines that are non-parallel to one another, but with each line remaining within ±5 degrees of perpendicular to the <1120> direction of a hexagonal crystal structure of a material of the substrate.