Patents Examined by Christine A Enad
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Patent number: 11757024Abstract: A semiconductor device and method for fabricating a semiconductor device includes etch selectivity tuning to enlarge epitaxy process windows. Through modification of etching processes and careful selection of materials, improvements in semiconductor device yield and performance can be delivered. Etch selectivity is controlled by using dilute gas, using assistive etch chemicals, controlling a magnitude of bias power used in the etching process, and controlling an amount of passivation gas used in the etching process, among other approaches. A recess is formed in a dummy fin in a region of the semiconductor where epitaxial growth occurs to further enlarge the epitaxy process window.Type: GrantFiled: April 7, 2021Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shih-Yao Lin, Te-Yung Liu, Chih-Han Lin
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Patent number: 11757019Abstract: A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.Type: GrantFiled: February 14, 2022Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Shih-Yao Lin, Chih-Han Lin, Shu-Uei Jang, Ya-Yi Tsai, Shu-Yuan Ku
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Patent number: 11756834Abstract: A semiconductor structure includes a first metal gate structure and a second metal gate structure. The first metal gate structure includes a first high-k gate dielectric layer, a first work function metal layer over the first high-k gate dielectric layer, and an N-containing barrier layer between the first high-k gate dielectric layer and the first work function metal layer. The second metal gate structure includes a second high-k gate dielectric layer and a second work function metal layer over the second high-k gate dielectric layer. The first high-k gate dielectric layer and the second high-k gate dielectric layer include a same metal material. The first high-k gate dielectric layer has a first metal concentration, the second high-k gate dielectric layer has a second metal concentration, and the first metal concentration is less than the second metal concentration.Type: GrantFiled: January 28, 2021Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Chien-Hao Chen
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Patent number: 11757040Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, first and second source/drain regions arranged on the fin-type active region; a first source/drain contact pattern connected to the first source/drain region and including a first segment having a first height in a vertical direction, a second source/drain contact pattern connected to the second source/drain region and including a second segment having a second height less than the first height in the vertical direction, and an insulating capping line extending on the gate line in the second horizontal direction and including an asymmetric capping portion between the first segment and the second segment, the asymmetric capping portion having a variable thickness in the first horizontal direction.Type: GrantFiled: January 6, 2022Date of Patent: September 12, 2023Inventors: Deokhan Bae, Juhun Park, Myungyoon Um, Kwangyong Jang
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Patent number: 11749739Abstract: A field-effect transistor (FET) device having a modulated threshold voltage (Vt) includes a source electrode, a drain electrode, a channel region extending between the source electrode and the drain electrode, and a gate stack on the channel region. The gate stack includes an ultrathin dielectric dipole layer on the channel region configured to shift the modulated Vt in a first direction, a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, and a doped gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction.Type: GrantFiled: August 6, 2021Date of Patent: September 5, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Wei-E Wang, Mark S. Rodder
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Patent number: 11749745Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate, and a first dielectric layer, a first gate structure and a plurality of second gate structures over the substrate. A second protection layer is formed on a top of a second gate structure. A first source-drain doped layer is formed between the first gate structure and an adjacent second gate structure. The first dielectric layer covers sidewalls of the first and second gate structures, and exposes a top surface of the second protection layer. The semiconductor structure also includes a first conductive structure in the first dielectric layer over the first source-drain doped layer, and a conductive layer on the first gate structure and the first conductive structure. A top surface of the conductive layer is coplanar with a top surface of the first dielectric layer.Type: GrantFiled: April 1, 2021Date of Patent: September 5, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Xiang Hu
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Patent number: 11742281Abstract: A semiconductor device may include a multi-level wiring structure comprising a first-level wiring layer, a second-level wiring layer and an insulating layer between the first-level wiring layer and the second-level wiring layer. The device may also include a bond pad, a first wiring extending from the bond pad, and a second wiring overlapping at least in part with the first wiring through the insulating layer to be capacitively coupled to the first wiring. The first wiring and the second wiring may each be formed respectively as the first-level wiring layer and the second-level wiring layer. The device may also include a protection circuit configured to be DC coupled to the second wiring. The first-level wiring layer may include a redistribution layer (RDL).Type: GrantFiled: January 21, 2021Date of Patent: August 29, 2023Assignee: Micron Technology, Inc.Inventors: Takashi Ishihara, Wataru Nobehara
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Patent number: 11742416Abstract: A semiconductor structure includes: a semiconductor substrate; a first source/drain feature and a second source/drain feature over the semiconductor substrate; and semiconductor layers extending longitudinally in a first direction and connecting the first source/drain feature and the second source/drain feature. The semiconductor layers are spaced apart from each other in a second direction perpendicular to the first direction. The semiconductor structure further includes inner spacers each between two adjacent semiconductor layers; metal oxide layers interposing between the inner spacers and the semiconductor layers; and a gate structure wrapping around the semiconductor layers and the metal oxide layers.Type: GrantFiled: May 27, 2021Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Hao Lin, Chia-Hung Chou, Chih-Hsuan Chen, Ping-En Cheng, Hsin-Wen Su, Chien-Chih Lin, Szu-Chi Yang
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Patent number: 11735665Abstract: A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.Type: GrantFiled: July 8, 2022Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Shan Lu, Chung-I Yang, Kuo-Yi Chao, Wen-Hsing Hsieh, Jiun-Ming Kuo, Chih-Ching Wang, Yuan-Ching Peng
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Patent number: 11735669Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor disposed over the first transistor. The first transistor includes a plurality of channel members vertically stacked over one another, and a first source/drain feature adjoining the plurality of channel members. The second transistor includes a fin structure, and a second source/drain feature adjoining the fin structure. The semiconductor device further includes a conductive feature electrically connecting the first source/drain feature and the second source/drain feature.Type: GrantFiled: November 11, 2020Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Yi Chuang, Hou-Yu Chen, Kuan-Lun Cheng
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Patent number: 11735425Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a metal gate disposed over the semiconductor fin. The semiconductor device includes a gate dielectric layer disposed between the semiconductor fin and the metal gate. The semiconductor device includes first spacers sandwiching the metal gate. The first spacers have a first top surface and the gate dielectric layer has a second top surface, and the first top surface and a first portion of the second top surface are coplanar with each other. The semiconductor device includes second spacers further sandwiching the first spacers. The second spacers have a third top surface above the first top surface and the second top surface. The semiconductor device includes a gate electrode disposed over the metal gate.Type: GrantFiled: March 7, 2022Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu Ang Chiang, Ming-Hsi Yeh, Chun-Neng Lin, Jian-Jou Lian, Po-Yuan Wang, Chieh-Wei Chen
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Patent number: 11728244Abstract: A semiconductor device includes a substrate, a semiconductor fin, a source/drain structure, a first buried power line, a contact, a first through substrate via (TSV), and a second TSV. The substrate has a well region extending a frontside surface of the substrate into the substrate. The semiconductor fin is on the well region. The source/drain structure is on the semiconductor fin. The first buried power line is electrically coupled to the source/drain structure on the first semiconductor fin. The first buried power line has a length extending along a lengthwise direction of the first semiconductor fin and a height extending within the well region. The first TSV extends from a backside surface of the substrate through the substrate to the first buried power line. The second TSV extends from the backside surface of the substrate to the well region.Type: GrantFiled: March 9, 2021Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Marcus Johannes Henricus Van Dal, Gerben Doornbos
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Patent number: 11728342Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes first and second gate patterns that are spaced apart from each other in a first direction on a substrate and extend in the first direction, a separation pattern that is disposed between and being in direct contact with the first and second gate patterns and extends in a second direction intersecting the first direction, a third gate pattern that is spaced apart in the second direction from the first gate pattern and extends in the first direction, and an interlayer dielectric layer disposed between the first gate pattern and the third gate pattern. The separation pattern includes a material different from a material of the interlayer dielectric layer. A bottom surface of the separation pattern has an uneven structure.Type: GrantFiled: April 13, 2022Date of Patent: August 15, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Hyun Park, Heonjong Shin
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Patent number: 11721699Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.Type: GrantFiled: January 25, 2021Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wan-Yi Kao, Hung Cheng Lin, Chunyao Wang, Yung-Cheng Lu, Chi On Chui
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Patent number: 11721695Abstract: A semiconductor structure includes a substrate, a semiconductor fin protruding from the substrate, where the semiconductor fin includes semiconductor layers stacked in a vertical direction, a gate stack engaging with channel regions of the semiconductor fin, and source/drain (S/D) features disposed adjacent to the gate stack in S/D regions of the semiconductor fin. In the present embodiments, the gate stack includes a first portion disposed over the semiconductor layers and a second portion disposed between the semiconductor layers, where the first portion includes a work-function metal (WFM) layer and a metal fill layer disposed over the WFM layer and the second portion includes the WFM layer but is free of the metal fill layer.Type: GrantFiled: July 16, 2021Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Jhon Jhy Liaw
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Patent number: 11721700Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction. The gate structure includes a first portion and a second portion separated by the gate isolation structure and the dielectric fin. The first portion of the gate structure presents a first beak profile and the second portion of the gate structure presents a second beak profile. The first and second beak profiles point toward each other.Type: GrantFiled: June 23, 2021Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Yao Lin, Chih-Han Lin, Ming-Ching Chang, Shu-Yuan Ku, Tzu-Chung Wang
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Patent number: 11715670Abstract: A method includes depositing a first work function layer over a first and second gate trench. The method includes depositing a second work function layer over the first work function layer. The method includes etching the second work function layer in the first gate trench while covering the second work function layer in the second gate trench, causing the first work function layer in the first gate trench to contain metal dopants that are left from the second work function layer etched in the first gate trench. The method includes forming a first active gate structure and second active gate structure, which include the first work function layer and the metal dopants left from the second work function layer in the first gate trench, and the first work function layer and no metal dopants left behind from the second work function layer, respectively.Type: GrantFiled: July 9, 2021Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yu-Chi Pan, Kuo-Bin Huang, Ming-Hsi Yeh, Ying-Liang Chuang, Yu-Te Su, Kuan-Wei Lin
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Patent number: 11705460Abstract: A panel comprises a substrate; a transistor disposed on the substrate and including: a source electrode, a drain electrode, a gate electrode, a gate insulation layer, an active layer, an auxiliary source electrode configured to electrically connect one end of the active layer to the source electrode, and an auxiliary drain electrode configured to electrically connect an other end of the active layer to the drain electrode; and a capacitor disposed on the substrate and including a first plate and a second plate. The first plate of the capacitor is made of a same material as the auxiliary source electrode and the auxiliary drain electrode.Type: GrantFiled: February 14, 2022Date of Patent: July 18, 2023Assignee: LG Display Co., Ltd.Inventors: Kwanghwan Ji, HongRak Choi, Jeyong Jeon, Jaeyoon Park
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Patent number: 11699702Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor in a first area and a second transistor in a second area. The first transistor includes a first gate structure extending lengthwise along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer over sidewalls of the first gate structure. The second transistor includes a second gate structure extending lengthwise along the first direction, and the first gate spacer and the third gate spacer over sidewalls of the second gate structure. The first gate spacer, the second gate spacer and the third gate spacer are of different compositions and the third gate spacer is directly on the first gate spacer in the second area.Type: GrantFiled: September 18, 2020Date of Patent: July 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sung-Hsin Yang, Jung-Chi Jeng, Ru-Shang Hsiao
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Patent number: 11699637Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a first set of transistor fins and a first set of contact metallization. An upper device layer is bonded onto the lower device layer, where the upper device layer includes a second structure comprising a second set of transistor fins and a second set of contact metallization. At least one power isolation wall extends from a top of the upper device layer to the bottom of the lower device layer, wherein the power isolation wall is filled with a conductive material such that power is routed between transistor devices on the upper device layer and the lower device layer.Type: GrantFiled: December 9, 2021Date of Patent: July 11, 2023Assignee: Intel CorporationInventors: Aaron D. Lilak, Anh Phan, Patrick Morrow, Stephanie A. Bojarski