Abstract: A process application layer receives a command that define a generic test for an application under test. A test code generator transforms the command into test engine instructions that exercise the generic tests on the application under test.

Abstract: A device receives a model that includes blocks and lines provided between the blocks, and identifies first candidate boundaries for the model. Each of the first candidate boundaries defines a group of blocks. The device generates an intermediate representation (IR) of the model, performs an optimization of the IR to generate an optimized IR, and identifies second candidate boundaries for the model based on the optimized IR. Each of the second candidate boundaries defines a group of blocks, and the first and second candidate boundaries define a set of candidate boundaries. The device reduces the set of candidate boundaries, to a reduced set of boundaries, based on code efficiency metrics or metrics associated with a hardware platform. The device generates code for the model based on the reduced set of boundaries, and outputs the code.

Abstract: According to embodiments of the invention, methods, computer readable storage medium, and a computer system for controlling access to variables protected by an alias are disclosed. The method may include monitoring, during a debug session, each attempt by a debugger to apply an operator to one or more variables protected by an alias. The method may also include determining whether to allow an application of an operator to a variable protected by an alias, wherein the determination is based at least in part on one or more rules.

Abstract: Software product build information is bi-directionally linked. At least a first build instance of the software product is built and the first build instance is published by a supplier build repository. Responsive to an entity who is not the supplier indicating a use of the first build instance in a client product, build information relating to the use of the first build instance in the client product is received. The build information relating to the use of the first build instance in the client product is published by the supplier build repository.

Abstract: An information processing apparatus includes a storage unit that stores combination information relevant to combinations of different types of first programs that can be installed in a device, the combination information including memory consumption amounts of the combinations; a receiving unit that receives an install target first program and device information relevant to the device; and a determining unit that determines validity of installing the install target first program in the device by determining, by referring to the combination information, a predicted memory consumption amount corresponding to a first combination including the install target first program and an existing first program that is installed in the device and indicated in the device information, and by comparing the predicted memory consumption amount with a device memory consumption amount of the device indicated in the device information.

Abstract: The embodiments may include an apparatus for measuring code quality using exceptions. The apparatus may include a runtime collector configured to intercept exceptions generated by an application, and collect exception information for each exception, during runtime of the application, based on instrumentation code included within the application. The apparatus may include a collection module configured to store the intercepted exceptions and corresponding exception information in a memory unit, an exception analyzer configured to analyze the intercepted exceptions based on the collected exception information stored in the memory unit, and a report generator configured to generate at least one report based on the analysis. The at least one report may provide an indication of code quality of the application.

Abstract: A device and method automatically generate a program for buffering differences based on characteristics of a component. A buffer program for buffering differences of the way to use a component during different software environments is automatically generated. The device includes a controller for executing automatic generation of the buffer program, a memory including control information and a processing program, an input device for inputting the processing content of the component, and an output device for outputting the automatically generated buffer program. The memory records a plurality of forms for buffering the component as the control information and the controller extracts characteristic information based on the processing content of the component and records the extracted characteristic information as control information in the memory, selects a specified form based on the characteristic information, and generates the buffer program based on the selected form and the characteristic information.

Abstract: An information processing apparatus includes a storage unit that stores reboot necessity information for respective versions of programs that are install targets of an electronic device, the reboot necessity information indicating whether the electronic device needs to be rebooted when a first program of a first version installed in the electronic device is updated to a second program of a second version; an extracting unit that extracts difference information indicating a difference between the first program and the second program in response to a request to acquire the second program, the request specifying the first version of the first program; a determining unit that determines whether the electronic device needs to be rebooted when the second program is installed, based on the difference between the first version and the second version indicated in the difference information and the reboot necessity information; and a responding unit that returns a determination result.

Abstract: A compiler implemented by a computer performs optimized division of work across heterogeneous processors. The compiler divides source code into code sections and characterizes each of the code sections based on pre-defined criteria. Each of the code sections is characterized as at least one of: allocate to a main processor, allocate to a processing element, allocate to one of a parameterized main processor and a parameterized processing element, and indeterminate. The compiler analyzes side-effects and costs of executing the code sections on allocated processors, and transforms the code sections based on results of the analyzing. The transforming includes re-characterizing the code sections for alternate execution in a runtime environment.

Abstract: Methods for identifying and analyzing performance traces are provided. Temporal logic formulas are patterns that can be compared with traces and individual events to identify the existence of certain behavior. Traces, sequences of time-stamped events in time order, are compared with one or more temporal logic formulas to identify the event sequences that match the formulas. The temporal logic formulas can be written in the simple temporal logic language that is presented. When a formula matches an event sequence, attributes from the event sequence are extracted and metric expressions are evaluated based on these attributes. The extracted attributes and the results of the metric expression are returned. This temporal logic pattern matching process can efficiently identify and analyze performance traces and significantly reduce manual effort for identifying performance problems.

Abstract: Techniques are described for unifying static and dynamic compiler optimizations in source code bases. In an embodiment, a first compiler compiles source code of a target function to generate ahead-of-time (AOT) compiled machine code. A second compiler compiles the source code to generate an intermediate representation (IR) of the target function. In response to determining that the target function should be just-in-time (JIT) compiled, the AOT-compiled machine code for the target function is linked to the IR of the target function. During runtime, a physical processor executes AOT-compiled machine code of an executable program. When the target function is encountered for the first time, a JIT compiler is invoked. The JIT compiler generates JIT-compiled machine code for the target function. The physical processor executes the JIT-compiled machine code in place of the AOT-compiled machine code for the target function.

Abstract: A plan to modify a software system is analyzed to identify objects of a first entity that are affected by the plan. An impact on a first part of the system is determined. Software modifications of a second entity in a second part of the system that are associated with the affected objects of the first entity are identified. Usage statistics of the first entity relating to the affected objects and usage statistics of the second entity relating to the software modifications are identified. An impact of the modifications to the affected objects on the software modifications of the second entity is determined. A first estimate of an effort to implement the modifications to the system is developed. A business blueprint is developed for the second entity. A trace of the affected objects and a trace of software executables are generated. A test plan is generated using the traces.

Abstract: A method and apparatus to enable SystemVerilog based tools to compile, debug, and execute a standardized testing language based test bench. The testing harness comprises, in one embodiment, a translator to map TTCN-3 language to a SystemVerilog test bench, a Verilog syntax compiler and simulator database including the mapped TTCN-3 language data, and a run time system using the SystemVerilog test bench with the database including the mapped TTCN-3 language data.