Abstract: A microprocessor based infrared (IR) decoding system operating with binary data including data bits preceded by synchronizing bits has an input flip flop for triggering a counter responsive to a synchronizing bit and activating a latch type flip flop a predetermined time later for interrogating the data and storing the data bit. The counter also operates another flip flop which signals the microprocessor that a data bit is in the latch. The microprocessor is thus able to process the data in the latch in a time interval ending just before occurrence of the next data bit. The counter triggers the input flip flop to reset and rearm the counter before the next synchronizing bit.

Abstract: A modular unitary disk file subsystem is used directly with a host computer. The subsystem includes a common unitary mounting substrate for power and signal connections to the host and for supplying control and data signals back via data, address and control buses to the host computer through a direct plug-in connection without any cabling between the subsystem and the host. The substrate carries and interconnects a unitary disk store head and disk assembly, a disk store control, a disk file controller, and a data and control interface with the computer. The modular unitary plugin form factor, a single supervisory microcomputer controller and a memory containing basic input/output driver routines directly executable by the host computer allow the subsystem to be transported easily between host computers.

Abstract: In a data processing system in which access to a second unit by a first unit through a system bus is determined by an arbitration unit, when a requesting unit that receives access to the system bus is unable to use that access for interaction with the second unit, a busy signal is provided to the arbitration unit and to the units. The busy signal causes the units to reinstitute a request for access to the system bus when the subsystem had an aborted transaction. The busy signal enforces a delay in the next arbitration for the system bus until a unit, with an aborted transaction as a result of the busy signal, can reassert the request for access signal. Moreover, apparatus can be included with the arbitration unit that permits rearbitrating access to the bus using the priority conditions in effect at the time of the original arbitration.

Abstract: An electronic postage meter employs a membrane switch mechanism. The postage meter is of the type having a mechanism for printing postage and accounting circuits for accounting for postage printed by the printing mechanism. A membrane switch is coupled between the printing mechanism and accounting circuits to provide print wheel setting information to the accounting circuits. The membrane switch mechanism may in one embodiment include a plurality of switch contacts and a plurality of switch contact actuating structures to activate different ones of the switch contacts. The membrane switch is mounted such that different ones of the plurality of the actuating structure activates a predetermined one of the plurality of switch contacts depending upon the position of the print wheels.

Abstract: A branch prediction for predicting, prior to executing a given branch instruction, whether the branch condition of the given branch instruction will be established, utilizes an address of an instruction that precedes the given branch instruction to access the branch prediction information for the given branch instruction from a branch prediction table.

Abstract: An arrangement, for adapting the serial interface of a data processing system to the data speed of a communication partner, has a recognition circuit for recognizing the transmission speed wherein signals from the communication partner having the unknown transmission speed are inputted to a frequency counter of the recognition circuit and the resulting count provided to a microprocessor which calculates an adjustment division signal N from the counting results. The adjustment divison signal N is inputted to a frequency divider of a phase lock loop (PLL) circuit of an adjustment circuit to provide a divided clock frequency signal which is compared with a divided reference frequency signal by the PPL circuit so that the frequency of a voltage control oscillator of the PLL circuit is adjusted until the divided clock frequency signal and divided reference frequency signal are equal.

Abstract: The communications adapter provides an interface between automotive vehicle on-board computer and a test computer running diagnostic software. Using a dual-ported random access memory, the circuit receives serial data from the on-board computer, preprocesses that data into a standardized data format, and places the standardized data directly into the memory space of the test computer. The dual-ported memory may be placed at a user selected address within the memory space of the test computer, so that it will not conflict with the diagnostic program running on the test computer. The invention is readily upgradable by uploading preprocessor software into random access memory, thereby making the invention upwardly compatible as new makes and models are introduced.

Abstract: A pipelined computer includes an instruction cache connected to an instruction prefetch queue for storing a target address and a target instruction, with the address of a branch instruction taken as an index, and a comparator for comparing a predicted target address stored in the instruction cache with a real target address determined upon execution of the branch instruction. When both the target addresses agree in the comparator, the decoding unit and the instruction prefetch queue continue pipeline processing without alteration.

Abstract: In a microcomputer system, having independently programmed tasks and a master control processing unit (CPU), tasks can be switched independent of the master CPU through the use of a multi-task support processor which may, for example, be connected to the microcomputer system via an input/output (I/O) port. The multi-task support processor includes a memory for storing task control programs, a data memory and task control memory, a timer, a controller for controlling multi-task operations, and a master CPU interface element. Tasks including task control commands are stored in a memory for execution by the master CPU. The master CPU, upon encountering a task control command, sends that command to the multi-task support processor which becomes activated to control the switching and communications between the tasks under the direction of the received task control command, so that tasking control may be performed independent of the master CPU.

Abstract: A speech analyzer is adapted to produce speech parameter signals from a Pth order autocorrelation analysis of a speech pattern in a digital signal processor. The analyzer includes a plurality of memories of predetermined arrangement to store feature vector signals used in the analysis, a single set of coded signals for controlling the analysis, and a memory address processor for addressing the feature vector signal memories. In each iteration of the analysis, at least one speech parameter signal is produced by the digital signal processor responsive to the same set of control signals and the feature vector memory addressing signals.

Abstract: An information transfer system for transferring binary information between a central unit and modular peripheral assemblies via a bus system. The bus system is designed as a serial ring shift register. An interface unit which permits parallel transfer of the individual binary information is interposed between the peripheral assembly and the bus.

Abstract: A storage control device is connected between a number of access request control units and a storage device including a number of memory units. The apparatus includes a number of transmission units, each corresponding to one of the access request control unit. Each transmission unit receives access requests from its associated access request control unit and divides the access requests into a number of groups in the order of issuance from the access request control units. The transmission units also add access request identifiers to the access requests in each group and transmit a number of access requests with access request identifiers to a number of access request deciders. Each access request decider is associated with one of the independently accessible memory units. Each decider receives the access requests directed to its associated memory unit and serially supplies the requests to that memory unit.

Abstract: A method for transmitting two independent types of information over a transmission path having a transmitter side and a receiver side, a storage unit and a multiplexer device including sampling and time-compressing a first information type on the transmitter side by means of a fast clock for generating time gaps, and transmitting the first information type on the transmitting path, transmitting a second information type within the time gaps over the transmission path, the first and second information type is read on the receiver side and recovered by time expansion using a slow clock. The first signal is interim-stored on the receiver side under the control of the slow clock and by generation of the time gap, under control of the fast clock frequency.

Abstract: Multiple processing systems each inclue an administrator processor and a plurality of intelligent resources (like a printer, encoder, for example) which are coupled to the associated administrator processor via a local area network (LAN). Each administrator processor is coupled to two pluralities or sets of intelligent resources with one set being connected through a primary connection node of the associated administrative processor and with the other set being connected to an associated secondary connection node. Each administrator processor is also directly coupled to exactly two other administrator processors through its associated primary and secondary connection nodes to form a closed ring network. An intelligent resource normally assigned to one administrator processor may be assigned (if available) to an adjacent administrator processor to reallocate the workload in the ring network and adjust to certain failures in the system.

Abstract: In a system that (i) defines each word in a vocabulary by a fenemic baseform of fenemic phones, (ii) defines an alphabet of composite phones each of which corresponds to at least one fenemic phone, and (iii) generates a string of fenemes in response to speech input, the method provides for converting a word baseform comprised of fenemic phones into a stunted word baseform of composite phones by (a) replacing each fenemic phone in the fenemic phone word baseform by the composite phone corresponding thereto; and (b) merging together at least one pair of adjacent composite phones by a single composite phone where the adverse effect of the merging is below a predefined threshold.

Abstract: In a parallel data processing system having a plurality of separately operating arithmetic processing units, a method and apparatus allows a plurality of branch instructions to be operated upon in a single machine cycle. The branch instructions have associated therewith a hierarchical priority system and the method and apparatus determine which branch, if any, should be taken. In particular, the method and apparatus simultaneously determine, during the parallel execution of the branch instructions, whether any branch test condition associated with a branch instruction is true, and independently, the target address for each branch instruction and a fall-through instruction address if a branch instruction is not taken.

Abstract: Apparatus and method for evaluating the likelihood of an event (such as a word) following a string of known events, based on event sequence counts derived from sparse sample data. Event sequences--or m-grams--include a key and a subsequent event. For each m-gram is stored a discounted probability generated by applying modified Turing's estimate, for example, to a count-based probability. For a key occurring in the sample data there is stored a normalization constant which preferably (a) adjusts the discounted probabilities for multiple counting, if any, and (b) includes a freed probability mass allocated to m-grams which do not occur in the sample data. To determine the likelihood of a selected event following a string of known events, a "backing off" scheme is employed in which successively shorter keys (of known events) followed by the selected event (representing m-grams) are searched until an m-gram is found having a discounted probability stored therefor.

Abstract: A process and a circuit arrangement for the automatic direct addressing of any desired memory location in the memories of a plurality of data processing units interconnected through a common bus by use of a single-step addressing technique is disclosed. The size of the memories used in the various processing units may be different. Addresses may be internally stored in the memories according to one of two addressing schemes. In a data processing unit initiating a data transmission connection, the external memory address of the desired memory location to be addressed is generated from an internally stored address and is transmitted to the bus system. This external address is received in each data processing unit, which performs an address calculation to determine whether the specified external address is within its volume or range of addresses.

Abstract: Speaker adaptation which enables a person to use a Hidden Markov model type recognizer previously trained by another person or persons. During initial training, parameters of Markov models are calculated iteratively by, for example, using the Forward-Backward algorithm. Adapting the recognizer to a new speaker involves (a) storing and utilizing intermediate results or probabilistic frequencies of a last iteration of training parameters, and (b) calculating new parameters by computing a weighted sum of the probabilistic frequencies stored during training and frequencies obtained from adaptation data derived from known utterances of words made by the new speaker.

Abstract: A vector processor having a vector register made up of elements of l.sub.2 -byte size for storing vector data made up of a plurality of elements read out from a main storage which has a plurality of storage areas and is capable of reading out data of l.sub.1 -byte size beginning from a specified address bound, and adapted to write vector data with an element size of m (l.sub.1 /m is an integer and l.sub.2 is larger or equal to m) into the vector register sequentially, read-out vector data from the vector register for computation by an arithmetic unit, and write the computational result into the vector register, wherein the processor writes elements of vector data read out from the main storage into separatte, specified locations of the vector register in an order required for subsequent operations.