Abstract: A memory includes a memory cell array unit, a plurality of memory cell bit lines connected to the memory cell array unit, a plurality of column selecting gates, and a plurality of sub data lines connected to the memory cell bit lines via the column selecting gates. A column selector serves to select and make conductive members of the column selecting gates so that data can be transmitted between successive members of the memory cell bit lines and the sub data lines. The memory further includes N-bit main data lines, where N denotes a given natural number. In addition, the memory includes data line selecting gates. The sub data lines are connected to the main data lines via the data line selecting gates. A data line selector serves to select and make conductive members of the data line selecting gates so that data can be transmitted between N successive members of the sub data lines and the main data lines.

Abstract: A device for coding key cards for magnetically operating locks and the incorporating of such a device which is as simple as possible plus the corresponding key cards in an entrance control system. The key card has, in addition to the locking code, a second identity coding, both of the codings being produced, insofar as possible, in a single passage through the device.

Abstract: A method and apparatus for synchronizing a plurality of processors. Each processor runs off of its own independent clock, indicates the occurrence of a prescribed process or event on one line and receives signals on another line for initiating a processor wait state. Each processor has a counter which counts the number of processor events indicated since the last time the processors were synchronized. When an event requiring synchronization is detected by a sync logic circuit associated with the processor, the sync logic circuit generates the wait signal after the next processor event. A compare circuit associated with each processor then tests the other event counters in the system and determines whether its associated processor is behind the others. If so, the sync logic circuit removes the wait signal until the next processor event. The processor is finally stopped when its event counter matches the event counter for the fastest processor.

Abstract: A card reader receives electronic chip cards of different thicknesses incing relatively thick and thin chip cards, each card having electrical interface connection terminals thereon. The reader includes a front panel having a card introduction opening. A first mating connector is positioned to engage the interface connection terminals of the thick chip cards. A fixed first guide positions the interface connection terminals of the thick cards into engagement the first mating connector. A second mating connector is positioned to engage the interface connection terminals of the thin chip cards. A moveable second guide means guides the interface connection terminals of the thin chip cards into engagement with the second mating connector. The second guide is retractable under action of introduction of the thick cards against a resilient return means.