Patents Examined by Christopher Young
  • Patent number: 9152038
    Abstract: Methods and structures for forming anodization layers that protect and cosmetically enhance metal surfaces are described. In some embodiments, methods involve forming an anodization layer on an underlying metal that permits an underlying metal surface to be viewable. In some embodiments, methods involve forming a first anodization layer and an adjacent second anodization layer on an angled surface, the interface between the two anodization layers being regular and uniform. Described are photomasking techniques and tools for providing sharply defined corners on anodized and texturized patterns on metal surfaces. Also described are techniques and tools for providing anodizing resistant components in the manufacture of electronic devices.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: October 6, 2015
    Assignee: Apple Inc.
    Inventors: Lucy Elizabeth Browning, Richard P. Howarth, Peggy Jensen, John Polley
  • Patent number: 9152037
    Abstract: The present invention provides a pattern correction method of, when a plurality of pattern elements on a mask used to process a line pattern formed on a substrate are transferred to the substrate, performing proximity effect correction of each pattern element such that a transferred image obtains a dimension equal to a target dimension, comprising setting, based on a density of a pattern element in a peripheral region surrounding a pattern element of interest, a dimension of the pattern element whose transferred image formed under the density of the pattern element has a dimension equal to the target dimension as a reference value for the pattern element of interest, and calculating a dimension of transferred image of the pattern element of interest while changing around the reference value and determining the dimension of the pattern element of interest based on the calculation result.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: October 6, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Ryo Nakayama
  • Patent number: 9146458
    Abstract: An EUV exposure apparatus according to embodiments includes a reticle stage which suctions a rear surface side of an EUV mask to retain the EUV mask. In addition, the EUV exposure apparatus includes a detection unit which detects a position of a measurement mark formed on the rear surface of the EUV mask in the state where the EUV mask is suctioned on the reticle stage. In addition, the EUV exposure apparatus includes a control unit which calculates a distortion amount of the EUV mask based on the position of the measurement mark and performs exposure control on a wafer while correcting the distortion amount.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 29, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshinori Hagio, Yosuke Okamoto
  • Patent number: 9146459
    Abstract: A low EUV reflectivity mask includes a low thermal expansion material (LTEM) layer, a low EUV reflectivity (LEUVR) multilayer over the LTEM layer in a first region, a high EUV reflectivity (HEUVR) multilayer over the LTEM layer in a second region and a patterned absorption layer over the LEUVR multilayer and the HEUVR multilayer.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: September 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9140975
    Abstract: A method of forming an improved EUV mask and pellicle with airflow between the area enclosed by the mask and pellicle and the area outside the mask and pellicle and the resulting device are disclosed. Embodiments include forming a frame around a patterned area on an EUV mask; forming a membrane over the frame; and forming holes in the frame.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: September 22, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Sun, Chanro Park, Wenhui Wang, Hui Zang
  • Patent number: 9134633
    Abstract: The present disclosure provides a method for fabricating a semiconductor structure. The method comprises providing a substrate and a patterned layer formed on the substrate, one or more overlay marks being formed on the patterned layer; performing a pre-film-formation overlay inspection using a bright field (BF) inspection tool to receive a pre-film-formation data on the one or more overlay marks on the patterned layer; forming one or more layers on the patterned layer; performing a post-film-formation overlay inspection using a dark field (DF) inspection tool to receive a post-film-formation data on the one or more overlay marks underlying the one or more layers; and determining whether the pre-film-formation data matches the post-film-formation data.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: September 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Jiun Lin, Hsin-Chieh Yao, Hai-Ching Chen, Tien-I Bao
  • Patent number: 9134604
    Abstract: A Cu-containing material is provided as an absorber layer of an EUV mask. With the absorber layer of the Cu-containing material, the same lithography performance of a conventional absorber in 70 nm thickness of TaBN can be achieved by only a 30-nm thickness of the absorber layer according to the various embodiments of the present disclosure. Furthermore, the out-off-band (OOB) flare of the radiation light in 193-257 nm can be reduced so as to achieve the better lithography performance.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: September 15, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tsung Shih, Hsin-Chieh Yao, Shinn-Sheng Yu, Jeng-Horng Chen, Chung-Ju Lee, Anthony Yen
  • Patent number: 9134615
    Abstract: An exposure method for an LCD glass substrate is revealed and includes: providing at least two photo masks, wherein each the photo mask includes active and inactive area with alignment-precision measurement-and-check marks disposed around the active area; performing exposure with each the photo mask on a separate reference substrate at a corresponding position, performing measurement of the alignment-precision measurement-and-check marks formed on the reference substrate, determining whether to modify a parameter of the exposure based on the measurement result, and obtaining accurate exposure parameter of each the photo mask; and combining the accurate exposure parameter of each the photo mask, using the combined exposure parameter to perform exposure sequentially with the at least two photo masks on the same substrate at corresponding positions, thereby obtaining an exposed pattern.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: September 15, 2015
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Yanfeng Fu
  • Patent number: 9134616
    Abstract: Techniques for reducing the number of shots required by a radiation beam writing tool to write a pattern, such as fractured layout design, onto a substrate. One or more apertures are employed by a radiation beam writing tool to write a desired pattern onto a substrate using L-shaped images, T-shaped images, or some combination of both. By reducing the number of shots required to write a pattern onto a substrate, various implementations of the invention may reduce the write time and/or write complexity of the write process.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: September 15, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Emile Y. Sahouria, Steffen F. Schulze
  • Patent number: 9128385
    Abstract: The embodiments described herein relate to methods, devices, and systems for masking a substrate using a photomasking process. An adaptive photomask configured to generate a photomasking pattern in accordance with dimensions of a surface feature on substrate is described. The adaptive photomask can be used to create customized photomask patterns for individual substrates. Methods and devices described herein can be used in manufacturing processes where similar parts having slight differences due to built-in tolerances are manufactured. Methods and a devices described herein can also be used in manufacture processes involving masking of three-dimensional portions of a part. A photomasking system that includes a translational mechanism for scanning a substrate surface is described.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: September 8, 2015
    Assignee: Apple Inc.
    Inventor: Napthaneal Yuen Tan
  • Patent number: 9128388
    Abstract: A method of focus measurement of the embodiment irradiates exposure light from a first direction and projects first and second line-and-space patterns on a substrate. Further, exposure light is irradiated from a second direction and third and fourth line-and-space patterns are projected on the substrate. By measuring a distance between the first and third line-and-space patterns on the substrate, a sum of a dislocated amount caused by dislocation of focus and an overlap dislocation amount between the first and third line-and-space patterns is calculated as a first dislocated amount. Further, by measuring a distance between the second and fourth line-and-space patterns on the substrate, an overlap dislocation amount between the second and fourth line-and-space patterns is calculated as a second dislocation amount. Further, based on the first and second dislocation amounts, the focus dislocation amount is calculated.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: September 8, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuhiro Komine
  • Patent number: 9122175
    Abstract: A system and method for repairing a photolithographic mask is provided. An embodiment comprises forming a shielding layer over an absorbance layer on a substrate. Once the shielding layer is in place, the absorbance layer may be repaired using, e.g., an e-beam process to initiate a reaction to repair a defect in the absorbance layer, with the shielding layer being used to shield the remainder of the absorbance layer from undesirable etching during the repair process.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Boming Hsu, Tran-Hui Shen
  • Patent number: 9122165
    Abstract: Provided are a method of manufacturing graphene, carbon nanotubes, fullerene, graphite, or a combination thereof having a regulated resistance, and a material manufactured using the method.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: September 1, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeo-young Shim, Tae-han Jeon, Kun-sun Eom, Dong-ho Lee
  • Patent number: 9116444
    Abstract: In a case where a substrate is exposed to exposure light of a first wavelength band, an exposure coefficient, which is defined as an amount of fluctuation of an imaging characteristic of a projection optical system per unit of exposure energy, for the first wavelength band is calculated using data of the amount of fluctuation of the optical characteristic of the projection optical system. An exposure coefficient for a second wavelength band that is different from the first wavelength band is calculated using the exposure coefficient for the first wavelength band. In a case where the substrate is exposed to exposure light of the second wavelength band, the amount of fluctuation of the imaging characteristic of the projection optical system is calculated using the exposure coefficient for the second wavelength band.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: August 25, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Rika Takahashi, Atsushi Shigenobu
  • Patent number: 9116434
    Abstract: An electron beam exposure method includes the steps of: preparing an exposure mask having a plurality of opening patterns formed by dividing a drawing object pattern into exposable regions; and drawing the drawing object pattern by performing exposure with an electron beam passing through the opening patterns of the exposure mask. Each end portion serving as a joint in each opening pattern of the exposure mask is provided with a joining portion tapered in a width of the opening pattern. The exposure is performed in such a way that portions drawn through adjacent joining portions overlap each other.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: August 25, 2015
    Assignee: Advantest Corp.
    Inventors: Shinichi Hamaguchi, Masaki Kurokawa, Masahiro Takizawa
  • Patent number: 9104109
    Abstract: A method for forming a pattern on a surface using charged particle beam lithography is disclosed, where the shots in an ordered set of input shots are modified within a subfield to reduce either a thermal variation or a maximum temperature of the surface during exposure by the charged particle beam writer. A method for fracturing or mask data processing is also disclosed, where an ordered set of shots is generated which will expose at least one subfield of a surface using a shaped beam charged particle beam writer, and where a temperature or a thermal variation generated on the surface during the exposure of one subfield is calculated. Additionally, a method for forming a pattern on a surface with an ordered set of shots using charged particle beam lithography is disclosed, in which a blanking period following a shot is lengthened to reduce the maximum temperature of the surface.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: August 11, 2015
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Ryan Pearman, Anatoly Aadamov
  • Patent number: 9091930
    Abstract: The present disclosure provides a semiconductor lithography system. The lithography system includes a projection optics component. The projection optics component includes a curved aperture. The lithography system includes a photo mask positioned over the projection optics component. The photo mask contains a plurality of elongate semiconductor patterns. The semiconductor patterns each point in a direction substantially perpendicular to the curved aperture of the projection optics component. The present disclosure also provides a method. The method includes receiving a design layout for a semiconductor device. The design layout contains a plurality of semiconductor patterns each oriented in a given direction. The method includes transforming the design layout into a mask layout. The semiconductor patterns in the mask layout are oriented in a plurality of different directions as a function of their respective location.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hsu Chang, Nian-Fuh Cheng, Chih-Shiang Chou, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 9086634
    Abstract: According to one embodiment, a production method for a mask layout of an exposure mask includes evaluating a candidate layout by comparison between an imaged image group and a reference image group. The imaged image group is composed of a plurality of imaged images of patterns formed by performing lithography under a plurality of levels of exposure condition using the candidate layout. The reference image group is composed of a plurality of reference images produced by simulation on assumption of a plurality of levels of the exposure condition.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: July 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuko Kono, Kazuyuki Masukawa, Toshiya Kotani, Chikaaki Kodama, Yasunobu Kai
  • Patent number: 9081312
    Abstract: The present disclosure provides a method that includes forming a first resist layer on a substrate; forming a second resist layer over the first resist layer; and performing an electron-beam (e-beam) lithography exposure process to the first resist layer and the second resist layer, thereby forming a first latent feature in the first resist layer and a second latent feature in the second resist layer.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: July 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9081287
    Abstract: One embodiment relates to a method of measuring overlay errors for a programmable pattern, area-imaging electron beam lithography apparatus. Patterned cells of an overlay measurement target array may be printed in swaths such that they are superposed on patterned cells of a first (base) array. In addition, the overlay array may have controlled-exposure areas distributed within the swaths. The superposed cells of the overlay and base arrays are imaged. The overlay errors are then measured based on distortions between the two arrays in the image data. Alternatively, non-imaging methods, such as using scatterometry, may be used. Another embodiment relates to a method for correcting overlay errors for an electron beam lithography apparatus. Overlay errors for a pattern to be printed are determined based on within-swath exposure conditions. The pattern is then pre-distorted to compensate for the overlay errors. Other embodiments, aspects and features are also disclosed.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: July 14, 2015
    Assignee: KLA-Tencor Corporation
    Inventors: Walter D. Mieher, Allen Carroll