Abstract: A system includes at least one industrial control and automation field device and a remote terminal unit (RTU). The RTU includes input/output (I/O) terminals configured to be coupled to the field devices. The RTU also includes one or more I/O modules having one or more reconfigurable I/O channels configured to be coupled to the I/O terminals. Each reconfigurable I/O channel is configurable as an analog input, an analog input supporting digital communication, an analog output, an analog output supporting digital communication, a digital input, a digital output, and a pulse accumulator input. The RTU further includes at least one processing device configured to control a configuration of each of the one or more reconfigurable I/O channels.

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

Abstract: A vector reduction instruction is executed by a processor to provide efficient reduction operations on an array of data elements. The processor includes vector registers. Each vector register is divided into a plurality of lanes, and each lane stores the same number of data elements. The processor also includes execution circuitry that receives the vector reduction instruction to reduce the array of data elements stored in a source operand into a result in a destination operand using a reduction operator. Each of the source operand and the destination operand is one of the vector registers. Responsive to the vector reduction instruction, the execution circuitry applies the reduction operator to two of the data elements in each lane, and shifts one or more remaining data elements when there is at least one of the data elements remaining in each lane.

Abstract: In an embodiment, an apparatus includes: a fabric of a first communication protocol to communicate with an upstream agent in an upstream direction and to communicate with a plurality of downstream agents in a downstream direction; a switch coupled between the fabric and at least some of the plurality of downstream agents, the switch to couple to a primary interface of the fabric via a primary interface of the switch and to communicate with the fabric via the first communication protocol, the switch further including a sideband interface to interface with a sideband fabric of the first communication protocol; and the at least some downstream agents coupled to the switch via the sideband fabric, wherein the at least some downstream agents are to be enumerated with a secondary bus of a second communication protocol, and the switch device is to provide a transaction received from the upstream agent to a first downstream agent based on a bus identifier of the secondary bus with which the first downstream agent is

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

Abstract: An electronic device and a method for changing modes according to external devices connected through a universal serial bus (USB) and controlling the strength of signals communicated according to changed modes are provided. The method includes detecting a connection with an external device corresponding to booting of the electronic device, determining a mode of the electronic device according to the detected connection with the external device, varying a characteristic setting of an input output (IO) buffer to a certain strength corresponding to the determined mode, and communicating a signal at a strength corresponding to the varied setting.

Abstract: An inter-integrated circuit bus arbitration system includes a first master circuit, a second master circuit, an analog switch circuit, an initial state identification circuit, and a selection control circuit. When the first master circuit is initiated to transmit data, the initial state identification circuit generates a first initial pulse signal. When the second master circuit is initiated to transmit data, the initial state identification circuit generates a second initial pulse signal. If the first initial pulse signal leads the second initial pulse signal, the selection control circuit generates a first control signal to make the analog switch circuit establish electrical connections between the first master circuit and an external data line and an external clock line when receiving the first control signal.

Abstract: A processor including a decode unit to decode a versatile packed data compare instruction to indicate a first source packed data operand to include a first plurality of data elements, a second source packed data operand to include a second plurality of corresponding data elements. The instruction to indicate a source comparison operation indication operand to include comparison operation indicators each to indicate a potentially different comparison operation for a different corresponding pair of data elements from the first and second source operands. An execution unit, in response to the instruction, to store a result in a destination storage location indicated by the instruction. Result to include result indicators each to correspond to a different one of the comparison operation indicators. Each result indicator to indicate a result of a comparison operation, indicated by the corresponding comparison operation indicator, performed on the corresponding pair of data elements.

Abstract: A peripheral component interconnect express PCI-e network system having a processor for (a) assigning addresses to the PCI-e topology tree, comprising: traversing, at a given level and in a breadth direction, down-link couplings to an interconnection; ascertaining, at the level, which of the down-link couplings are connected to nodes; assigning, at the level, addresses to nodes of ascertained down-link coupling having nodes; and (b) propagating, a level, comprising: traversing, at the level and in a depth direction, down-link couplings to the interconnection of the PCI-e network, ascertaining, at the level, which of the downlink couplings are coupled to other interconnections in the depth direction, consecutively proceeding in the depth direction, to a next level of the down-link coupling of a next interconnection; and alternatively repeating (a) and (b) until the nodes are assigned addresses within the PCI-e tree topology network.

Abstract: Embodiments relate to non-interfering transactions. An aspect includes receiving, by a first transaction, a conflicting remote access request from a requester, the remote access request being directed to a memory area that is owned as part of at least one of a transactional read set and transactional write set by the first transaction. Another aspect includes determining whether the requester is a second transaction that is indicated as a non-interfering transaction with respect to the first transaction. Another aspect includes, based on determining that the requester is indicated as a non-interfering transaction with the first transaction, handling the remote access request. Yet another aspect includes continuing execution of the first transaction and the second transaction after handling the remote access request.

Abstract: Embodiments relate to non-interfering transactions. An aspect includes receiving, by a first transaction, a conflicting remote access request from a requester, the remote access request being directed to a memory area that is owned as part of at least one of a transactional read set and transactional write set by the first transaction. Another aspect includes determining whether the requester is a second transaction that is indicated as a non-interfering transaction with respect to the first transaction. Another aspect includes, based on determining that the requester is indicated as a non-interfering transaction with the first transaction, handling the remote access request. Yet another aspect includes continuing execution of the first transaction and the second transaction after handling the remote access request.

Abstract: A processor is described having a functional unit within an instruction execution pipeline. The functional unit having circuitry to determine whether substantive data from a larger source data size will fit within a smaller data size that the substantive data is to flow to.

Abstract: A memory management module receives a request to access a page in a memory, sends the request to a memory controller controlling the memory if the page is available in the memory, and if the page is unavailable, (i) does not send the request to the memory controller, and (ii) generates a first exception. A hypervisor intercepts the first exception and sends a second exception to an operating system. The operating system includes a handler to, in response to the second exception, selectively request the memory controller to obtain the page from a storage device into the memory, and to suspend execution of a first thread issuing the request on a processor until the page becomes available in the memory; and a kernel to schedule execution of a second thread on the processor until the page becomes available, or to idle the processor until the page becomes available.

Abstract: A control circuit of a memory device feeds a first clock received from a transmission control circuit of a host device back to a reception control circuit of the host device as a second clock. The reception control circuit controls data reception from the memory device in synchronization with the fed-back second clock.

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

Abstract: A Universal Serial Bus (USB) converter circuit includes: a High Definition Multimedia Interface (HDMI) transceiver circuit, a signal converting circuit and a USB receptacle, wherein the HDMI transceiver circuit arranged to transmit/receive a HDMI signal, wherein the HDMI transceiver circuit includes at least a video signal and a plurality of processing signals; the signal converting circuit coupled to the HDMI transceiver circuit is arranged to execute a converting operation to processing a conversion between the plurality of processing signals and A USB signal; and the USB receptacle coupled to the signal converting circuit includes a USB signal pin and a set of video signal pin, wherein the USB signal is transmitted/received with an electronic device through the USB pin, and the video signal is transmitted/received with the electronic device through the set of video signal pin.

Abstract: Operation of a PCIe Retimer over an Optical Cable has been disclosed. In one implementation a Optical Idle ordered set (OIOS) is introduced as well as a high Z ordered set (HZOS).

Abstract: In an example, a method of managing direct memory access (DMA) descriptors for commands to a non-volatile semiconductor storage device includes requesting DMA descriptors from the host system for each of a plurality of the commands stored in a command random access memory (RAM). The method further includes storing the DMA descriptors for each of the plurality of the commands in free descriptor regions in a descriptor RAM. The method further includes maintaining a dynamic descriptor list in the descriptor RAM for each of the plurality of commands, the dynamic descriptor list for each of the plurality of commands comprising occupied descriptor regions in the descriptor RAM having associated DMA descriptors.

Abstract: A smart harness may comprise a connector configured to selectively plug into and be removable from an Electronic Control Unit (“ECU”) of a vehicle, a first On-Board Diagnostics device (“first OBD device”), and a second On-Board Diagnostics device (“second OBD device”). The smart harness may further comprise at least one transceiver configured to receive and send diagnostic information between the ECU and the first OBD device and the second OBD device. The smart harness may further comprise a processor and a memory having a program communicatively connected to the processor.