Abstract: Providing efficient floating-point operations using matrix processors in processor-based systems is disclosed. In this regard, a matrix-processor-based device provides a matrix processor comprising a positive partial sum accumulator and a negative partial sum accumulator. As the matrix processor processes pairs of floating-point operands, the matrix processor calculates an intermediate product based on a first floating-point operand and a second floating-point operand and determines a sign of the intermediate product. Based on the sign, the matrix processor normalizes the intermediate product with a partial sum fraction of the positive partial sum accumulator or the negative partial sum accumulator, then adds the intermediate product to the positive sum accumulator or the negative sum accumulator.

Abstract: A method includes detecting noise in a laser output of a heat assisted magnetic recording device. The noise is converted into an electrical signal including a numerical value. A least significant digit of the numerical value is selected. The least significant digit is concatenated with another least significant digit from another detecting of another noise in another laser output to form a number.

Abstract: Setting or updating of floating point controls is managed. Floating point controls include controls used for floating point operations, such as rounding mode and/or other controls. Further, floating point controls include status associated with floating point operations, such as floating point exceptions and/or others. The management of the floating point controls includes efficiently updating the controls, while reducing costs associated therewith.

Abstract: Setting or updating of floating point controls is managed. Floating point controls include controls used for floating point operations, such as rounding mode and/or other controls. Further, floating point controls include status associated with floating point operations, such as floating point exceptions and/or others. The management of the floating point controls includes efficiently updating the controls, while reducing costs associated therewith.

Abstract: Methods, systems, and apparatus, including a system for transforming sparse elements to a dense matrix. The system is configured to receive a request for an output matrix based on sparse elements including sparse elements associated with a first dense matrix and sparse elements associated with a second dense matrix; obtain the sparse elements associated with the first dense matrix fetched by a first group of sparse element access units; obtain the sparse elements associated with the second dense matrix fetched by a second group of sparse element access units; and transform the sparse elements associated with the first dense matrix and the sparse elements associated with the second dense matrix to generate the output dense matrix that includes the sparse elements associated with the first dense matrix and the sparse elements associated with the second dense matrix.

Abstract: An aspect includes a direct digital synthesis system including a waveform generator with a waveform memory operable to store a plurality of waveform vectors and output a selected waveform vector. The direct digital synthesis system also includes a digital-to-analog converter operable to convert the selected waveform vector from a digital value to an analog signal responsive to a reference clock. The direct digital synthesis system further includes a controller operable to maintain phase continuity of the analog signal when an output of the analog signal is interrupted and restored.

Abstract: An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K? bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J? bits per word, wherein J? is less than N multiplied by K?.

Abstract: Multiple random numbers are generated. The multiple random numbers are N different random numbers. N is a positive integer. Generating the multiple random numbers includes generating a random number array including N storage units. The multiple random numbers are shuffled. A random number obtaining instruction is received. A random number is obtained from the multiple random numbers based on the random number obtaining instruction.

Abstract: Systems and methods for allowing analog Ising machines to be able to run Integer Linear Programming (“ILP”) problems, i.e. a compilation method for setting the state of the physical memory units, flexible to be adapted to each specific device. The method describes how variables and numeric parameters which specify the problem can be hard-coded (embedded and physically represented) in the hardware circuitry of the device in a deterministic way, with a pre-determined bound on the number of required physical spins to be used in the Ising device.

Abstract: A system for block floating point computation in a neural network receives a block floating point number comprising a mantissa portion. A bit-width of the block floating point number is reduced by decomposing the block floating point number into a plurality of numbers each having a mantissa portion with a bit-width that is smaller than a bit-width of the mantissa portion of the block floating point number. One or more dot product operations are performed separately on each of the plurality of numbers to obtain individual results, which are summed to generate a final dot product value. The final dot product value is used to implement the neural network. The reduced bit width computations allow higher precision mathematical operations to be performed on lower-precision processors with improved accuracy.

Abstract: The present invention relates to a computer-implemented method and a system for determining co-occurrences in at least one graph with n vertices and E edges, wherein each edge is defined by a pair of vertices, the method comprising: storing a binary adjacency matrix representing a first graph in a memory; performing a calculation step for the first graph, wherein the calculation step comprises: loading a block of at most K consecutive rows of the binary adjacency matrix from the memory and storing each row into one of K caches; streaming each of the subsequent uncached rows of the binary adjacency matrix from the memory; reading pairs of rows comprising a streamed row and each one of the cached rows; computing the logical conjunction between each couple of elements of the rows at the same position in the rows for each read pair of rows; and adding the results of the logical conjunction for all the couples of elements in each read pair by means of one-bit adders to obtain the co-occurrence, wherein the calcula

Abstract: According to some embodiments, a computer-implemented method for performing sparse matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) module comprising a k-stage pipeline is described. The method may include interleaving k-stage threads on the k-stage pipeline comprising a plurality of threads t0 to tk-1, wherein a first result of thread t0 is ready one cycle after the first input of thread tk-1 is fed into the pipeline, and outputting a result matrix Y.

Abstract: An ALU capable of generating a multiply accumulation by compressing like-magnitude partial products. Given N pairs of multiplier and multiplicand, Booth encoding is used to encode the multipliers into M digits, and M partial products are produced for each pair of with each partial product in a smaller precision than a final product. The partial products resulting from the same encoded multiplier digit position, are summed across all the multiplies to produce a summed partial product. In this manner, the partial product summation operations can be advantageously performed in the smaller precision. The M summed partial products are then summed together with an aggregated fixup vector for sign extension. If the N multipliers are equal to a constant, a preliminary fixup vector can be generated based on a predetermined value with adjustment on particular bits, where the predetermined value is determined by the signs of the encoded multiplier digits.

Abstract: The present embodiments relate to integrated circuits with floating-point arithmetic circuitry that handles normalized and denormalized floating-point numbers. The floating-point arithmetic circuitry may include a normalization circuit and a rounding circuit, and the floating-point arithmetic circuitry may generate a first result in form of a normalized, unrounded floating-point number and a second result in form of a normalized, rounded floating-point number. If desired, the floating-point arithmetic circuitry may be implemented in specialized processing blocks.

Abstract: Embodiments are directed to an integrated circuit for a low-power random number generator that uses a thin-film transistor. Embodiments of the integrated circuit include one or more front-end devices formed on a substrate, and one or more interlayer dielectric (ILD) layers formed on the one or more front-end devices. Embodiments of the integrated circuit also include one or more back-end devices formed on the one or more ILD layers, wherein the one or more back-end devices are configured to amplify a noise signal and transmit an amplified noise signal to the one or more front-end devices for processing.

Abstract: This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.

Abstract: Arithmetic circuits and methods that perform efficient conversion of fractional RNS representations to fractional binary representations is disclosed herein.

Abstract: Methods, systems, and apparatus for quantum phase estimation. In one aspect, an apparatus includes a quantum circuit comprising: a first quantum register comprising at least one ancilla qubit, a second quantum register comprising one or more qubits, wherein the second quantum register is prepared in a quantum state that is not an eigenstate of a unitary operator operating on the first and second quantum register; and a phase learning system, configured to learn phases of the eigenvalues of the unitary operator.

Abstract: Arithmetic circuits and methods that perform efficient matrix multiplication for hardware acceleration of neural networks, machine learning, web search and other applications are disclosed herein. Various arrays of multiplier-accumulators may be coupled to form a matrix multiplier which processes data using high precision, fixed point residue number arithmetic.

Abstract: A device for generating sum-of-products data includes an array of variable resistance cells, variable resistance cells in the array each including a transistor and a programmable resistor connected in parallel, the array including n columns of cells including strings of series-connected cells and m rows of cells. Control and bias circuitry are coupled to the array, including logic for programming the programmable resistors in the array with resistances corresponding to values of a weight factor Wmn for the corresponding cell. Alternatively, the resistances can be programmed during manufacture. Input drivers are coupled to corresponding ones of the m rows of cells, the input drivers selectively applying inputs Xm to rows m. Column drivers are configured to apply currents In to corresponding ones of the n columns of cells. Voltage sensing circuits operatively coupled to the columns of cells.