Abstract: A L2 cache for resolving collisions between processor request originating from a processor and system request originating from a computing unit attached to the system bus is provided. First, the L2 cache snoops a system request to access a shared resource. This shared resource is often an area of main memory contained in the L2 cache. Next, the L2 cache receives a processor request to access the shared resource also. The L2 cache will delay sending an acknowledge signal to the processor. The L2 cache then makes a determination as to whether the address and system request type must be sent to the processor. If data associated with the system request would alter a line in a L1 cache associated with the processor, a retry signal is sent to the processor. If the system request would not alter a line in the L1 cache, the L2 cache will wait until the system request finishes accessing the shared resource to process the processor request, thereby avoiding the sending of a retry signal to the processor.

Abstract: A snooper circuit of a multi-processor system includes a plurality of processor boards each having a central processing unit, a cache memory, a cache controller to control the cache memory and a snooper controller, a main memory, and a system bus for interconnecting these.

Abstract: A system and method for reducing the number of writeback operations performed by level two (L2) or higher level cache memories in a microprocessor system having an integrated hierarchical cache structure. Writeback operations of modified victim lines in L2 or higher level caches are cancelled if an associated cache line, having a "modified" status, is located in a lower level cache. In one embodiment of the present invention, writeback operations of modified victim lines in L2 or higher level caches are also cancelled if an associated cache line, having a "clean" status, is located in a lower level cache.

Abstract: An upgradeable cache circuit is described which automatically routes those control signals necessary to maintain cache coherency in a computer system having a processor (with integrated L1 cache) coupled with main memory by a controller. The cache circuit includes an L2 cache module connector and a high speed multiplexer having minimal propagation delay. The multiplexer selects one of two sets of control signals to route to and from the processor, controller and cache circuit, corresponding to the presence or absence of an L2 cache module in the cache module connector.

Abstract: A computer network connects information providers and end-users of network services, facilitates direct information to users, and gathers user responses. The computer network is designed to use otherwise idle bandwidth of the network transmission medium to transfer targeted commercial and non-commercial information to users while minimizing the delay of normal network traffic. User reports containing demographics and user responses is generated ensuring user privacy. Information providers can access the user report without violating user anonymity.

Abstract: Accordingly, a computer implemented method, uniquely programmed computer system, and article of manufacture embodying computer readable program means all allow a customer on an external network to initiate an authorized business transaction utilizing internal business resources on an internal network without violating security firewalls. Specifically, the method directs an internal computer system to allow an external computer system to initiate a transaction request using internal resources without violating a security firewall between the internal computer system and the external computer system. The method includes a first step of authenticating a connection initiated by the internal computer system between the internal computer system and the external computer system, thereby establishing an authenticated connection. The second step includes calling by the external computer system a transaction request received by the external computer system.

Abstract: An information processing device includes a central processing unit, a cache memory unit and first and second decision circuits. The first decision circuit identifies one of partitioned address areas to be accessed before the central processing unit accesses the cache memory unit. The second decision circuit determines whether the above one of the partitioned address areas is a cachable area or a non-cachable area before address tag data is referred to in the cache memory unit.

Abstract: An integrated circuit (10) includes a memory (20) which has a plurality of memory modes, including a high density memory mode and a high speed/reliability memory mode. The high speed/reliability memory mode may alternately be used as a high reliability memory mode. Memory (20) includes a configuration circuit (80) which selects one of the plurality of memory modes. Configuration circuit (80) provides configuration information to sense amplifier control circuit (72). Sense amplifier control circuit (72) provides control information to sense amplifiers (70) in order to place sense amplifiers (70) in one of a plurality of operating modes. In one embodiment, the plurality of operating modes of sense amplifiers (70) includes a complementary differential operating mode and a referenced differential operating mode.

Abstract: The present invention is directed, in general, to network connectivity, and more specifically to circuits and methods for intelligent acknowledgment-based flow control in a processing system network. The present invention concerns governing transmission of data packets and reception indicia by a transmission circuit over a network. Detector circuitry is included and is operative to (1) monitor a first latency characteristic of the network that is indicative, at least in part, of a utilization level of the network; and (2) monitor a second latency characteristic indicative, at least in part, of an efficiency level associated with transmission of the reception indicia by the transmission circuit. Control circuit is further included and is associated with the detector circuitry and the transmission circuit.

Abstract: Effective memory management maximizes the use of main memory in a computing system by avoiding the issuance of operating system primitives which result in overhead and increased processing time. This allows an applications program to change the state of a storage unit such as a buffer or page without requiring the issuance of an operating system primitive to change the physical state of the storage unit. A storage manager is provided for controlling the movement of data between storage units in secondary storage and storage units in main memory. A storage unit state indicator or flag is associated with each storage unit in main memory. In addition, a system state indicator for indicating the physical state of a storage unit is also associated with each storage unit. The system state indicator may be set to one of the states of fixed or pageable while the storage unit state indicator may be set to one of the states of fixed, pageable or don't care.

Abstract: An upgradeable cache circuit is described which automatically routes those control signals necessary to maintain cache coherency in a computer system having a processor (with integrated LI cache) coupled with main memory by a controller. The cache circuit includes an L2 cache module connector and a high speed multiplexer having minimal propagation delay. The multiplexer selects one of two sets of control signals to route to and from the processor, controller and cache circuit, corresponding to the presence or absence of an L2 cache module in the cache module connector.

Abstract: A memory architecture and method of partitioning a computer memory. The architecture includes a cache section, a setup table, and a compressed storage, all of which are partitioned from a computer memory. The cache section is used for storing uncompressed data and is a fast access memory for data which is frequently referenced. The compressed storage is used for storing compressed data. The setup table is used for specifying locations of compressed data stored within the compressed storage. A high speed uncompressed cache directory is coupled to the memory for determining if data is stored in the cache section or compressed storage and for locating data in the cache.

Abstract: A method, apparatus and article of manufacture for managing pages of virtual storage in a computer system by delaying the actual release of a page by the system after its release has been requested by a guest program of the system, resulting in pending page releases. Establishment of a pending page release results in an entry in a log of pending page release, leaving the page(s) allocated to the guest. The system can release pages in the log at any time. The guest can request cancellation of pending page releases, in which case the requested pages are removed from the log for reuse by the guest if they have not already been released by the system. Key setting, page clearing or formatting, and page validation or staging, are optional services which can be included in cancellation requests. Establishment and cancellation are preferably requested by the guest using the intercepted instruction DIAGNOSE, and are performed by a storage manager component of the host operating system.

Abstract: A digital data storage subsystem stores data for use by digital data utilization device. The data as used by the digital data utilization device being organized in the form of variable-length records. The digital data storage subsystem includes a digital data storage device, a cache and a cache control. The digital data storage device has at least one fixed block storage unit for storing a predetermined amount of data, the storage unit storing at least one record and additional padding if the record does not comprise at least said predetermined amount of data. The cache including at least one cache slot which can accommodate the storage of the predetermined amount of data, that is, the amount which can be stored on the block storage unit of the digital data storage device.

Abstract: A load/store buffer is provided which allows both load memory operations and store memory operations to be stored within it. Memory operations are selected from the load/store buffer for access to the data cache, including cases where the memory operation selected is subsequent in program order to a memory operation which is known to miss the data cache and is stored in the buffer. In this way, other memory operations that may be waiting for an opportunity to access the data cache may make such accesses, while the memory operations that have missed await an opportunity to make a main memory request. Memory operations that have missed are indicated by a miss bit being set, so that the mechanism which selects memory operations to access the data cache may ignore them until they become non-speculative.

Abstract: In a distributed shared memory computer system a plurality of workstations are connected to each other by a network. Each workstation includes a processor, a memory having addresses, and an input/output interface connected to each other by a bus. The input/output interfaces connect the workstations to each other by the network. In a software implemented method for batching access checks to shared data stored in the memories, a set of the addresses of the memories are designated virtual shared addresses to store shared data. A portion of the virtual shared addresses is allocated to store a shared data structure as one or more lines accessible by instructions of the programs executing in any of the processors, the size of each line being a predetermined number of bytes. The programs are analyzed to locate a set of instructions of a particular program which access a range of target addresses storing shared data, the range of target addresses being no greater than the size of one line.

Abstract: A software implemented method for lock-up free data sharing operates in a networked computer system including a plurality of workstations. Each workstation including a processor, a memory having addresses, and an input/output interface connected to each other by a bus. A set of addresses of the memories are designated as virtual shared addresses to store shared data. A portion of the virtual shared addresses is allocated to store the shared data as a plurality of blocks accessible by programs executing in any of the processors, each block including an integer number of lines. A program is instrumented to request an exclusive copy of the block if the program includes a store instruction which attempts to access data stored in a non-exclusive copy of the block. Additional instructions of the program are executed while the request for the exclusive copy of the block is pending. Addresses of data of the block modified by the additional instructions are recorded.

Abstract: A multi-tier cache system and a method for implementing the multi-tier cache system is disclosed. The multi-tier cache system has a small cache in random access memory (RAM) that is managed in a Least Recent Used (LRU) fashion. The RAM cache is a subset of a much larger non-volatile cache on rotating magnetic media (e.g., a hard disk drive). The non-volatile cache is, in turn a subset of a local CD-ROM or of a CD-ROM or mass storage device controlled by a server system. In a preferred embodiment of the invention, a heuristic technique is employed to establish a RAM cache of optimum size within the system memory. Also in a preferred embodiment, the RAM cache is made up of multiple identically-sized sub-blocks. A small amount of RAM is utilized to maintain a table which implements a Least Recently Used (LRU) RAM cache purging scheme. A hashing mechanism is employed to search for the "bucket" within the RAM cache in which the requested data may be located.

Abstract: A cooperative activity system, in which a plurality of computer devices are connected via a network, performs an activity by cooperation among the computer devices. A server for recording data is connected to the network and monitors data transferred to the network, creates a keyword conforming to the type of data when the data is transferred and stores the keyword in a file. While data is not being generated, a keyword is created depending upon (1) whether a specific time has arrived, (2) the lapse of time spent in a certain length of a cooperative activity or (3) the passage of a prescribed period of time from an immediately preceding item of data, and both the keyword and the particular event are stored as a file. As a result, desired cooperative activity data can be read out by performing retrieval based upon the keyword.

Abstract: An interprise computing manager in which an application is composed of a client (front end) program which communicates utilizing a network with a server (back end) program. The client and server programs are loosely coupled and exchange information using the network. The client program is composed of a User Interface (UI) and an object-oriented framework (Presentation Engine (PE) framework). The UI exchanges data messages with the framework. The framework is designed to handle two types of messages: (1) from the UI, and (2) from the server (back end) program via the network. The framework includes a component, the mediator which manages messages coming into and going out of the framework.