Abstract: The yield of a separation process is improved. The mass productivity of a display device which is formed through a separation process is improved. A layer is formed over a substrate with use of a material including a resin or a resin precursor. Next, a resin layer is formed by performing heat treatment on the layer. Next, a layer to be separated is formed over the resin layer. Then, the layer to be separated and the substrate are separated from each other. The heat treatment is performed in an atmosphere containing oxygen or while supplying a gas containing oxygen.

Abstract: A semiconductor structure includes a substrate, a source/drain (S/D) junction, and an S/D contact. The S/D junction is associated with the substrate and includes a trench-defining wall, a semiconductor layer, and a semiconductor material. The trench-defining wall defines a trench. The semiconductor layer is formed over the trench-defining wall, partially fills the trench, substantially covers the trench-defining wall, and includes germanium. The semiconductor material is formed over the semiconductor layer and includes germanium, a percentage composition of which is greater than a percentage composition of the germanium of the semiconductor layer. The S/D contact is formed over the S/D junction.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Abstract: Interconnect structures and corresponding formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary interconnect structure for a FinFET includes a gate node via electrically coupled to a gate of the FinFET, a source node via electrically coupled to a source of the FinFET, and a drain node via electrically coupled to a drain of the FinFET. A source node via dimension ratio defines a longest dimension of the source node via relative to a shortest dimension of the source node via, and a drain node via dimension ratio defines a longest dimension of the drain node via relative to a shortest dimension of the drain node via. The source node via dimension ratio is greater than the drain node via dimension ratio. In some implementations, the source node via dimension ratio is greater than 2, and the drain node via dimension ratio is less than 1.2.

Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.

Abstract: Electric vehicles that use replaceable and exchangeable batteries and systems are provided. A system includes a battery carrier for holding a plurality of batteries. The battery carrier is connectable to a power source and the plurality of batteries are rechargeable and replaceable into and out of the battery carrier. The battery carrier includes slots for receiving the plurality of batteries and control systems for communicating over a network. The control systems are configured for identifying presence of batteries in the slots of the battery carrier and charge level of batteries present in the slots. The system further includes a server that communicates over the network with the control systems of the battery carrier. The server is part of a cloud system that manages access to user accounts. The user accounts are accessible via applications executed on user devices.

Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.

Abstract: A semiconductor device and method of making same. The semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.

Abstract: Wafer-level (chip-scale) package semiconductor devices are described that have bump assemblies configured to maintain standoff (bump) height. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having an array of bump assemblies disposed over the integrated circuit chip. The array of bump assemblies comprises a plurality of first bump assemblies that include solder bumps composed at least substantially of a solder composition (i.e., do not include a core). The array further includes at least one second bump assembly including a solder bump having a core configured to maintain standoff height of the wafer-level package device.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Abstract: Interactive product auditing with a mobile device is described. Example methods disclosed herein include performing, with an auditing device, image recognition based on a first set of candidate patterns accessed by the auditing device to identify a first product in a first region of interest of a segmented image. The disclosed example methods also include prompting, with the auditing device, a user to enter input associated with a first grid of the first region of interest displayed on a display, the first grid including the first product. The disclosed example methods further include determining, with the auditing device, a second set of candidate patterns to use to identify a second product in a second region of interest of the segmented image, the second set of candidate patterns determined based on the user input and a group of products identified in a neighborhood of the first region of interest.

Abstract: An embodiment is a method including bonding a first package to a first set of conductive pads of a second package with a first set of solder joints, testing the first package for defects, heating the first set of solder joints by directing a laser beam at a surface of the first package based on testing the first package for defects, after the first set of solder joints are heated, removing the first package, and bonding a third package to the first set of conductive pads of the second package.

Abstract: Aromatic resin polymers and compositions containing them are useful as underlayers in semiconductor manufacturing processes.

Abstract: Some embodiments provide methods and systems of controlling irrigation. Some of these systems comprise: a connector of a controller interface (CI) coupled with an irrigation controller, wherein the connector is configured to receive a valve activation signal activated by the irrigation controller; a user interface of the CI; a processor of the CI configured to obtain valve transceiver (VT) programming with VT programming being received from inputs through the user interface, determine a station identifier, and identify as defined in the VT programming a remote valve associated with the station identifier and controlled by a remote VT; and a wireless transceiver configured to wirelessly transmit a wireless activation signal configured to be wirelessly received by the VT controlling the valve associated by the VT programming with the station identifier such that the VT is configured to control an actuator to actuate the valve.

Abstract: A method of manufacturing customized ceramic labial/lingual orthodontic brackets by digital light processing, said method comprises measuring dentition data of a profile of teeth of a patient, wherein measuring dentition data is performed using a CT scanner or intra-oral scanner, based on the dentition data, creating a three dimensional computer-assisted design (3D CAD) model of the patient's teeth using reverse engineering, and saving the 3D CAD model on a computer, designing a 3D CAD bracket structure model for a single labial or lingual bracket structure, importing the 3D CAD bracket structure model into a Digital Light Processing (DLP) machine, directly producing the bracket by layer manufacturing.

Abstract: A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog output signal output from the analog circuit to digital conversion; a second semiconductor substrate in which the remaining part of the analog circuit and the digital circuit are formed; and a substrate connection portion which connects the first and second semiconductor substrates to each other. The substrate connection portion transmits an analog signal which is generated by a part of the analog circuit of the first semiconductor substrate to the second semiconductor substrate.

Abstract: The present disclosure relates to nanoscale device comprising an elongated crystalline nanostructure, such as a nanowire crystal, a nanowhisker crystal or a nanorod crystal, and a method for producing thereof. One embodiment relates to a nanoscale device comprising an elongated crystalline semiconductor nanostructure, such as a nanowire (crystal) or nanowhisker (crystal) or nanorod (crystal), having a plurality of substantially plane side facets, a crystalline structured first facet layer of a superconductor material covering at least a part of one or more of said side facets, and a second facet layer of a superconductor material covering at least a part of the first facet layer, the superconductor material of the second facet layer being different from the superconductor material of the first facet layer, wherein the crystalline structure of the semiconductor nanostructure is epitaxially matched with the crystalline structure of the first facet layer on the interface between the two crystalline structures.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Abstract: The exemplified methods and systems facilitates the configuring of IO devices and its IO modules (and submodules) in enabling an operator to retrieve, via a single input, in a development workspace, a list of IO modules and submodules that is compatible to a given IO device. The exemplified methods and systems facilitates retrieval of compatible IO modules and submodules based parameters of the IO modules and submodules. The exemplified methods and systems provide an intuitive interface, in a development workspace for configuring an IO device, to add a retrieved (i.e., searched) module or submodule from a list thereof to an existing project for a given IO device.

Abstract: An integrated circuit package including an integrated circuit component, a patterned dielectric liner, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component includes an active surface and conductive vias distributed on the active surface. The patterned dielectric liner conformally covers the active surface of the integrated circuit component and sidewalls of the conductive vias. The insulating encapsulation encapsulates sidewalls of the integrated circuit component and covers the patterned dielectric liner. The insulating encapsulation includes a planar top surface. The planar top surface of the insulating encapsulation is substantially coplanar with top surfaces of the conductive vias. The insulating encapsulation and the conductive vias are spaced apart by the patterned dielectric liner.