Abstract: The invention relates to a method for the production of an integrated circuit, comprising the following steps: a substrate (1) is provided with at least one first, second and third gate stack (GS1, GS2, GS3) of approximately the same height surface of said substrate, a common active area (60) being provided on the surface of the substrate in said substrate (1) between the first and second gate stack (GS1, GS2); a first insulating layer (70) is provided in order to cover the embedding of the first second and third gate stack (GS1, GS2, GS3); the upper side of a gate connection (20) of the third gate stack (GS3) is uncovered; a second insulating layer (80) is provided in order to cover the upper side of a gate connection (20); a mask (M2) is provided on the resulting structure having a first opening (12a) above the uncovered upper side of the gate connection (20) of the third gate stack (GS3), a second opening (F2b) above the substrate (1) between the third and second gate stack (GS3, GS2) and a third opening (

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Yet, aluminum wires have greater electrical resistance and are less reliable than copper wires. Unfortunately, current techniques for making copper wires are time-consuming and inefficient. Accordingly, the invention provides a method of making wires or interconnects from copper or other metals. One embodiment entails forming a first diffusion barrier inside a trench using ionized-magnetron sputtering for better conformal coating of the trench, and a second diffusion barrier outside the trench using jet-vapor deposition. The jet-vapor deposition has an acute angle of incidence which prevents deposition within the trench and thus eliminates conventional etching steps that would otherwise be required to leave the trench free of this material. After formation of the two diffusion barriers, the trench is filled with metal and annealed.

Abstract: A semiconductor device is formed including a substrate having an upper surface, a thyristor region in the substrate and a control port adapted for capacitively coupling to at least a portion of the thyristor region via a dielectric material. According to an example embodiment of the present invention, a trench is formed in the substrate and subsequently filled with materials including dielectric material and a control port. The control port is adapted for capacitively coupling to the thyristor via the dielectric material for controlling current flow in the thyristor (e.g., for causing an outflow of minority carriers from a portion of the thyristor for switching the thyristor from conducting state to a blocking state). A portion of the substrate adjacent to the upper surface is implanted with a species of ions, and the dielectric material via which the control port capacitively couples to the thyristor does not include the species of ions.

Abstract: A Thin Film Transistor (TFT) manufacture method, comprising manufacture of a gate, a gate isolation layer, a channel layer, and a source/drain. Wherein, the manufacture of the channel layer comprises: forming a first a-Si layer by using a low deposition rate (LDR) (Chemical Vapor Deposition, CVD); forming a second a-Si layer by using a high deposition rate (HDR); and forming an N+Mixed a-Si layer. When the first a-Si layer is formed in the present invention, the flux ratio of H2/SiH4 is adjusted to a range from 0.40 to 1.00 to increase the number of defects in the first a-Si layer. When the TFT is irradiated by the light, the photo leakage current generated in the channel layer is trapped in the defects in the first a-Si layer. Therefore, the TFT photo leakage current can be significantly reduced.

Abstract: This invention provides a semiconductor device with an element isolation implemented by a method of manufacturing a semiconductor device comprising the steps of: forming a pad oxide film 140 and a nitride film 150 sequentially on a silicon layer 130 in an element region S; forming a metal oxide film 180 for generating a fixed electric charge on the nitride film 150 and on the silicon layer 130 in an element isolation region A; forming a field oxide film 160 in the element isolation region A by implementing an oxidation treatment; and removing the metal oxide film 180 on the nitride film 150, the nitride film 150 and the pad oxide film 140. In the semiconductor device, the threshold voltage of a parasitic transistor is made high and prevented from turning on, and the influence of leak current is reduced and the hump characteristic of element is restrained.

Abstract: A high performance bipolar transistor device is realized from a series of layers formed on a substrate, the series of layers including a first set of one or more layers each comprising n-type dopant material, a second set of layers forming a p-type modulation doped quantum well structure, and a third set of one or more layers each comprising n-type dopant material. The first set of layers includes an n-type ohmic contact layer. A collector terminal metal layer is deposited and patterned on one layer of the third set. P-type ion implant regions and a patterned base terminal metal layer (which contact the p-type modulation doped quantum well structure) are formed in an interdigitated manner with respect to a patterned emitter metal layer formed on the n-type ohmic contact layer. Preferably, a capping layer that covers the sidewalls of the active device structure (as well as covering the collector metal layer) is used to form the interdigitated base and emitter metal layers of the device.

Abstract: A method for fabricating a CMOS image sensor including a low voltage buried photodiode and a transfer transistor, includes the steps of: forming a field oxide for defining active area and field area on certain area of an epitaxial layer formed on a substrate, and forming a gate of transfer transistor on the epitaxial layer of the active area; forming the low voltage buried photodiode doping region in alignment with one side of the gate of transfer transistor and field oxide; forming a spacer insulation layer by stacking layers of oxide and nitride over the whole structure; forming a spacer block mask to open areas excluding doping region for the low voltage buried photodiode; and removing the spacer block mask, and forming a floating diffusion region on other side of the transfer transistor. Alternatively, the sacrificial nitride may be allowed to remain on the surface of the photodiode to improve optical properties for short wavelength lights.

Abstract: In a molding process, a hybrid integrated circuit substrate is fixed the position of the substrate in a thickness direction. A leadframe is connected, with an upward inclination, to a hybrid integrated circuit substrate and transported into a mold cavity. By horizontally fixing the leadframe by mold dies, the hybrid integrated circuit substrate inclined upward is urged downward by a pushpin. This can fix the position of the hybrid integrated circuit substrate within the mold cavity and integrally transfer-molded.

Abstract: A method and apparatus for making an imprinted conductive circuit using semi-additive plating. A plurality of indented channels is formed on the substrate. The surface is coated with a conductive layer. Portions of the surface other than the indented channels are coated with a non-conductive layer, and metal is plated on the conductive layer in the channels. The non-conductive layer and the first conductive layer are removed from portions of the surface other than the indented channels. In some embodiments, a first set of channels has a first depth and a second set of channels has a second depth. The plating adds a first amount of metal in the first set of channels and the second set of channels. The first set of channels is coated with a non-conductive layer, and a second amount of additional conductive material is plated in the second set of channels.

Abstract: A method of fabricating a semiconductor device. A stack gate structure having a cap layer thereon and a first dielectric layer having a top surface that exposes the cap layer are formed on a substrate. A buffer layer is formed to cover the dielectric layer and the cap layers in a first region of the substrate. A portion of the cap layers in a second region of the substrate are removed so that the cap layers have a thickness smaller than or equal to the buffer layer. A second dielectric layer is formed over the substrate. A portion of the second dielectric layer and the underlying the buffer layer and the first dielectric layer are etched to form a bit line contact opening. In the meantime, a portion of the second dielectric layer and the underlying cap layer are etched to form a gate contact opening.

Abstract: The present invention allows non-wafer form devices to be tested on a standard automatic wafer-probe tester or other automated test or measurement device commonly employed in semiconductor or allied industries (e.g., flat panel display, data storage, or the like) processes. The present invention accomplishes this by providing a low-profile carrier for temporarily mounting a non-wafer form device. The low-profile carrier holds the non-wafer form device (e.g., an integrated circuit chip, a thin film head structure, one or more molded array packages, etc.) magnetically into recesses which are machined or otherwise formed in the low-profile carrier.

Abstract: The electronic device is formed in a die including a body of semiconductor material having a first face covered by a covering structure and a second face. An integral thermal spreader of metal is grown galvanically on the second face during the manufacture of a wafer, prior to cutting into dice. The covering structure comprises a passivation region and a protective region of opaque polyimide; the protective region and the passivation region are opened above the contact pads for the passage of leads.

Abstract: Described is a method wherein a seal ring is formed by patterning multiple layers each comprised of a dielectric layer with conductive vias covered by a conductive layer. Discontinuities are made in the seal ring encapsulating an integrated circuit. There are no overlaps between different sections of the seal ring thereby reducing coupling of high frequency circuits in the seal ring structures. In addition, the distance between signal pads, circuits and the seal ring are enlarged. Electrical connection is made between deep N-wells and the seal ring. This encapsulates the integrated circuit substrate and reduces signal coupling with the substrate.

Abstract: A semiconductor light emitting device includes a crystal layer formed on a substrate, the crystal layer having a tilt crystal plane tilted from the principal plane of the substrate, and a first conductive type layer, an active layer, and a second conductive type layer, which are formed on the crystal layer in such a manner as to extend within planes parallel to the tilt crystal plane, wherein the device has a shape formed by removing the apex and its vicinity of the stacked layer structure formed on the substrate. Such a semiconductor light emitting device is excellent in luminous efficiency even if the device has a three-dimensional device structure. The present invention also provides a method of fabricating the above semiconductor light emitting device.

Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

Abstract: In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

Abstract: A DRAM array in an SOI wafer having a uniform BOX layer extending throughout the array eliminates the collar oxide step in processing; connects the buried plates with an implant that, in turn, is connected to a conductive plug extending through the device layer and the box that is biased at ground; while the pass transistors are planar NFETs having floating bodies that have a leakage discharge path to ground through a grounded bitline.

Abstract: A new method is provided for the interconnection of flip chips to a supporting substrate. The invention starts with a conventional first substrate, that serves as a semiconductor device support structure, over the surface of which a first pattern of contacts points has been provided. The invention then uses a second substrate, for instance a glass or quartz plate, and creates over the surface thereof a second pattern of solder bumps separated by solder non-wettable surfaces. The second pattern is a mirror image of the first pattern. By then overlying the first pattern of contact points with the second pattern of solder bumps, a step of reflow can be applied to the solder bumps, transferring the solder bumps from the second substrate to the contact points provided over the first substrate.

Abstract: A flat panel display includes a pixel electrode having an opening portion formed on an insulating substrate, a semiconductor layer formed over a surface of the insulating substrate, spaced apart from the pixel electrode, having source and drain regions formed to both end portions thereof, a first insulating layer formed over the surface of the insulating substrate excluding the opening portion of the pixel electrode, a gate electrode formed on the first insulating layer over the semiconductor layer, and a second insulating layer formed over the surface of the insulating substrate excluding the opening portion of the pixel electrode. The present invention provides an organic EL display manufactured with reduced mask processes which has excellent electrical characteristics and improved light transmittance.

Abstract: A method, system and materials for use in hydrogen gettering in conjunction with microelectronic and microwave components that are generally hermetically sealed in an enclosure typically referred to as a “package”. Gettering materials that can be used include titanium with or without a hydrogen permeable coating or covering, alloys of zirconium-vanadium iron and zeolites and several ways to apply these materials to the package. In addition, the hydrogen permeable material can be used over a vent from the interior of the package to the exterior wherein hydrogen will escape from the package interior when the hydrogen concentration within the package is greater than without the package.