Patents Examined by Craig S Goldschmidt
  • Patent number: 11416166
    Abstract: Systems and methods for distributed storage and processing systems using estimate-based schedulers are described. A node receives estimated processing data for each storage device including redundant copies of data chunks for a data unit. The node determines, based on the estimated processing data and data paths to each data chunk, a task time estimate for data paths to each data chunk and selects data paths for at least one copy of each data chunk to be processed using a corresponding set of compute tasks. The compute tasks are sent for processing based on the assignments of the node.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: August 16, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Dinesh Kumar Agarwal
  • Patent number: 11392310
    Abstract: A memory system includes a memory device including a plurality of memory blocks, and a controller for controlling the memory device. The controller stores user data in an original block selected among the memory blocks. When the original block becomes a closed block, the controller generates a copy block by copying each page of the original block into a page having the same page address of a free block among the memory blocks, and stores map data associated with the user data in the memory device, the map data including a logical address of the user data, an address of the original block, an address of the copy block, and a common page address. The common page address is a page address which is in common in the original block and the copy block. In embodiments, the controller limits the number of copy blocks according to a configurable copy level.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: July 19, 2022
    Assignee: SK hynix Inc.
    Inventor: Hungyung Cho
  • Patent number: 11379392
    Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: July 5, 2022
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Kenneth Lee Wright
  • Patent number: 11372548
    Abstract: Some systems compress data utilized by a user mode software without the user mode software being aware of any compression taking place. To maintain that illusion, such systems prevent user mode software from being aware of and/or accessing the underlying compressed states of the data. While such an approach protects proprietary compression techniques used in such systems from being deciphered, such restrictions limit the ability of user mode software to use the underlying compressed forms of the data in new ways. Disclosed herein are various techniques for allowing user-mode software to access the underlying compressed states of data either directly or indirectly. Such techniques can be used, for example, to allow various user-mode software on a single system or on multiple systems to exchange data in the underlying compression format of the system(s) even when the user mode software is unable to decipher the compression format.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 28, 2022
    Assignee: NVIDIA Corporation
    Inventors: Ram Rangan, Patrick Richard Brown, Wishwesh Anil Gandhi, Steven James Heinrich, Mathias Heyer, Emmett Michael Kilgariff, Praveen Krishnamurthy, Dong Han Ryu
  • Patent number: 11354063
    Abstract: A memory system includes a plurality of non-volatile memory chips divided into a plurality of storage areas, and a memory controller that is connected to the plurality of memory chips to control an operation of each memory chip. The memory controller is configured to set an arbitration period separately for each of the respective storage areas, and to execute a process to store data into the storage areas one after another in accordance with the arbitration period set therefor.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 7, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Tetsuhiko Azuma
  • Patent number: 11334246
    Abstract: Subscriber-managed nanoservices enable the states of multiple instances of an object to be contemporaneously updated without requiring an object-wide mutex or per-instance dedicated threads. A separate subscriber-managed nanoservice is implemented for each object instance. Each subscriber-managed nanoservice includes a first function that adds requests to update state of an object instance to a FIFO queue and provides a lock to only one subscriber thread at a time. Each subscriber-managed nanoservice includes a second function that combines queued requests and performs object instance state updates response to calls from the lock-holding subscriber thread. Each subscriber-managed nanoservice functions independently so multiple instances of an object can be contemporaneously updated. Further, it is not necessary to have a dedicated thread for management of each object instance because the subscriber threads call the functions.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: May 17, 2022
    Assignee: Dell Products L.P.
    Inventor: Thomas Watson
  • Patent number: 11327671
    Abstract: One example method of operation may include identifying event block allocations of one or more of data memory and data storage allocations, assigning indicators to the event block allocations based one or more determined statuses associated with the event block allocations, populating a display interface with the event block allocations and the indicators, performing a trace event of the event block allocations, identifying a target event block allocation among the event block allocations, and creating a notification identifying an allocation violation based on the identified target event block allocation.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: May 10, 2022
    Assignee: Two Six Labs, LLC
    Inventor: Huy Vu
  • Patent number: 11320999
    Abstract: A system and method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices with DRAM memory controllers such as field programmable gate arrays (FPGAs). The DRAM memory controller is utilized in concert with a data maintenance block collocated with the DRAM memory and coupled to an I2C interface of the reconfigurable device, wherein the FPGA drives the majority of the DRAM input/output (I/O) and the data maintenance block drives the self-refresh command inputs. Even though the FPGA reconfigures and the majority of the DRAM inputs are tri-stated, the data maintenance block provides stable input levels on the self-refresh command inputs.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 3, 2022
    Assignee: FG SRC, LLC
    Inventor: Timothy J. Tewalt
  • Patent number: 11301379
    Abstract: An access request processing method is performed by a computer device that includes a processor, a dynamic random-access memory (DRAM), and a non-volatile memory (NVM). When receiving a write request, the processor may identify an object cache page according to the write request. The processor obtains the to-be-written data from a buffer according to a buffer pointer in the write request, the to-be-written data including a new data chunk to be written into the object cache page. The processor then inserts a new data node into a log chain of the object cache page, where the NVM stores data representing the log chain of the object cache page. The new data node includes information regarding the new data chunk of the object cache page. The computer device provided in this application can reduce system overheads while protecting data consistency.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: April 12, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jun Xu, Qun Yu, Yuangang Wang
  • Patent number: 11294710
    Abstract: A processing system suspends execution of a program thread based on an access latency required for a program thread to access memory. The processing system employs different memory modules having different memory technologies, located at different points in the processing system, and the like, or a combination thereof. The different memory modules therefore have different access latencies for memory transactions (e.g., memory reads and writes). When a program thread issues a memory transaction that results in an access to a memory module having a relatively long access latency (referred to as “slow” memory), the processor suspends execution of the program thread and releases processor resources used by the program thread. When the processor receives a response to the memory transaction from the memory module, the processor resumes execution of the suspended program thread.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: April 5, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Douglas Benson Hunt
  • Patent number: 11287976
    Abstract: Techniques involve: in response to adding a second set of disks into a redundant array of independent disks (RAID) including a first set of disks and a total number of disks in the first and second sets exceeding a predetermined threshold, determining types and numbers of disks in the first and second sets, respectively; determining, based on the types and numbers of the disks determined and a performance indicator of the RAID having the added second set, respective types and numbers of disks comprised in a plurality of sets to which the disks in the RAID are to be allocated; and performing, based on the type and number of disks in the first set and the respective types and numbers of disks, an allocation of a disk in the first set to one of the plurality of sets, until all the disks in the first set have been allocated.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 29, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Rongrong Shang, Ruiyong Jia, Shuai Ni, Sihang Xia, Zhenhua Zhao
  • Patent number: 11275517
    Abstract: A device implementing a system for reducing an amount of metadata stored with respect to updates to data includes a processor configured to receive a first sequence of identifiers comprising identifiers which are unique with respect to each other and which represent first updates to data, and a second sequence of identifiers comprising identifiers which are unique with respect to each other and which represent second updates to the data, the first and second updates to the data being independent of one another. The processor is further configured to generate a third sequence of identifiers comprising identifiers which are unique with respect to each other and with respect to the identifiers in at least one of the first or second sequences of identifiers, the third sequence of identifiers representing a combination of the first and second sequences of identifiers, and to provide for storage of the third sequence of identifiers.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: March 15, 2022
    Assignee: Apple Inc.
    Inventor: William J. Thimbleby
  • Patent number: 11249895
    Abstract: A memory controller for preventing the storage area of a flash memory being reduced is provided. The memory controller controlling access to a flash memory based on a command provided from a host system, the memory controller includes: a processor, a RAM (random access memory), and a mask ROM (read only memory) in which a first firmware is written, wherein the memory controller is configured to: perform a search for a second firmware written in the flash memory based on the first firmware at a start-up time; and write a third firmware provided from the host system in the RAM when the second firmware is not found through the search and perform an initialization based on the third firmware written in the RAM.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 15, 2022
    Assignee: TDK CORPORATION
    Inventors: Naoki Mukaida, Kenichi Takubo
  • Patent number: 11237966
    Abstract: Synchronization events associated with cache coherence are monitored without using invalidations. A callback-read is issued to a memory address associated with the synchronization event, which callback-read either reads the last value written in the memory address or blocks until a next write takes place in the memory address and reads a newly written value.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 1, 2022
    Assignee: ETA SCALE AB
    Inventors: Stefanos Kaxiras, Alberto Ros
  • Patent number: 11237735
    Abstract: A method for storing data includes establishing an extended generation group comprising a plurality of data sets. The plurality of data sets includes a first data set containing primary members and a first number of generations of each of the primary members, and a second data set containing a second number of generations of each of the primary members. The method further indicates, in the metadata of the first data set, a maximum number of generations allowable in each of the first and second data sets When a primary member is modified in the first data set, the method automatically moves an oldest generation in the first data set to the second data set, and deletes an oldest generation in the second data set to ensure that the extended generation group does not exceed the maximum number.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: February 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Derek L. Erdmann, David C. Reed, Thomas C. Reed, Max D. Smith
  • Patent number: 11199993
    Abstract: There has been desired a technology for performing a publishing setting of a variable to an external device more easily. A development assistance device provides a development tool configured to develop a user program for controlling a controller. The user program includes at least one variable belonging to a predetermined namespace. The development tool is configured to accept, for the namespace, a publishing setting for causing the controller to determine whether to publish the variable belonging to the namespace to an external device that is communicatively connected to the controller. A communication interface transfers the user program and the publishing setting to the controller on the basis of acceptance of transfer operation of the user program by the development tool.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: December 14, 2021
    Assignee: OMRON Corporation
    Inventors: Fumiaki Konishi, Yuta Nagata
  • Patent number: 11175829
    Abstract: Methods, apparatus, and processor-readable storage media for automatic identification of workloads contributing to behavioral changes in storage systems using machine learning techniques are provided herein. An example computer-implemented method includes obtaining a primary time series and a set of candidate time series; calculating, using machine learning techniques, similarity measurements between the primary time series and each candidate time series in the set; for each similarity measurement, assigning weights to the candidate time series based on similarity values; generating, for each candidate time series, a similarity score based on the assigned weights; automatically identifying, based on the similarity scores, a candidate time series as contributing to an anomaly exhibited in the primary time series; and outputting identifying information of the at least one identified candidate time series for use in one or more automated actions associated with the storage system.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: November 16, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Fatemeh Azmandian, Peter Beale, Bina K. Thakkar, Zachary W. Arnold
  • Patent number: 11175838
    Abstract: Methods, apparatus, and processor-readable storage media for automatic identification of resources in contention in storage systems using machine learning techniques are provided herein.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: November 16, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Fatemeh Azmandian, Peter Beale, Bina K. Thakkar, Zachary W. Arnold
  • Patent number: 11175854
    Abstract: A producer processing unit of a data processing system that is producing a stream of data for use by one or more consumer processing units of the data processing system maintains a record that is accessible to the consumer processing units of a position in the data stream for which it has written data to memory. The consumer processing units then control their reading of the data stream from the memory in accordance with the write position record maintained by the producer processing unit.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 16, 2021
    Assignee: Arm Limited
    Inventors: Erik Persson, Stefan Johannes Frid, Philip Gregory Hall, Dominic Hugo Symes, Sven Ola Johannes Hugosson, Robert Norberg
  • Patent number: 11150830
    Abstract: File access statistics associated with a content file are maintained by a file tier agent of a secondary storage system. The content file is accessible via a primary storage system. A target storage tier corresponding to the file access statistics associated with the content file is determined according to one or more policies. At least a portion of data of the content file is migrated to the determined storage tier while accessibility of the content file via the primary storage system is maintained.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: October 19, 2021
    Assignee: Cohesity, Inc.
    Inventors: Zheng Cai, Vijay Pasikanti, Ganesha Shanmuganathan