Abstract: An OLED device capable of emitting multiple colors is disclosed. In one embodiment of the invention, multiple substrates are stacked upon one another, wherein the different substrates emit light of a given color. In another embodiment of the invention, these substrates are separated by spacer particles to prevent the overlying substrates from contacting the active components.

Abstract: A system for delivering power to an integrated circuit includes a decoupling capacitance located in a connector that is formed as a socket, or frame for the IC. The power delivery system takes the form of a power reservoir that is integrated into a connector, thereby eliminating the need for complex and expensive power traces to be formed in or discrete capacitors mounted on a circuit board to which the IC is connected. The system includes a connector that takes the form of a cover member that fits over the IC and which contains a recess that accommodates a portion of the IC therein. The cover member includes at least a pair of spaced-apart capacitor plates that are disposed therewithin. Electricity is supplied to the plates so that they will become charged as a capacitor and the plates are formed with a plurality of terminals that extend into contact with the IC so that the plates may selectively discharge to the IC and thereby provide it with operating and surge currents.

Abstract: A ball grid array integrated circuit package is manufactured by mounting a semiconductor die, to a surface of a substrate such that bumps on the semiconductor die are electrically connected to conductive traces of the substrate. At least one collapsible spacer is mounted to at least one of a heat spreader, the semiconductor die and the substrate. The heat spreader is fixed to the at least one of the first surface of the substrate and the semiconductor die such that he at least one collapsible spacer is disposed therebetween. A ball grid array is formed on a second surface of the substrate, bumps of the ball grid array being electrically connected to the conductive traces and the integrated circuit package is singulated.

Abstract: Metal nitride and metal oxynitride extrusions often form on metal silicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract: The invention provides bumps between a die and a substrate with a height greater than or equal to a height of a waveguide between the die and the substrate. The bumps may be formed on a die prior to that die being singulated from a wafer.

Abstract: Provided is a compound semiconductor substrate fabrication method involving: preparing a base substrate; forming a first buffer layer on the prepared base substrate; forming a semiconductor layer on the first buffer layer; and removing the base substrate.

Abstract: The described embodiments relate to substrates having features formed therein and methods of forming same. One exemplary method forms a blind feature through a majority of a thickness of a substrate, the blind feature being defined by at least one sidewall surface and a bottom surface. The method also applies an etch resistant material to the blind feature and removes the etch resistant material from at least a portion of the bottom surface. The method further wet etches the substrate at least through the bottom surface sufficient to form a through feature through the thickness of the substrate.

Abstract: A method for producing a semiconductor component includes coating a substrate with a metalization. The metalization is structured in such a way that interconnects are formed at least in an encapsulation region. An encapsulation is applied in the encapsulation region around a previously applied chip. In order to provide sealing during the application of the encapsulation, either the interconnects are structured in such a way that they are interconnected, or a labyrinth structure is formed between the interconnects.

Abstract: A manufacturing method of a flip chip package mainly comprises the following steps. Initially, a chip having an active surface with a plurality of bumps formed thereon is provided. Next, the active surface of the chip is faced to and disposed on an upper surface of a substrate. In such manner, the chip will be electrically connected to the substrate and a gap between the chip and the substrate will be formed. Afterwards, an underfill is filled in the gap and then a first curing process is performed to have the underfill partially hardened to have the underfill transformed into a partially hardened underfill. Finally, the combination of the chip, the substrate and the partially hardened underfill is flipped over to have the substrate located above the chip, then a second curing process is performed to have the partially hardened underfill into a fully hardened underfill, and then flipping over the combination of the chip, the substrate and the fully hardened underfill.

Abstract: Integrated microreactor, formed in a monolithic body and including a semiconductor material region and an insulating layer; a buried channel extending in the semiconductor material region; a first and a second access trench extending in the semiconductor material region and in the insulating layer, and in communication with the buried channel; a first and a second reservoir formed on top of the insulating layer and in communication with the first and the second access trench; a suspended diaphragm formed by the insulating layer, laterally to the buried channel; and a detection electrode, supported by the suspended diaphragm, above the insulating layer, and inside the second reservoir.

Abstract: An interconnection wiring system incorporating two levels of interconnection wiring separated by a first dielectric, a capacitor formed by a second dielectric, a bottom electrode of the lower interconnection wiring or a via and a top electrode of the upper interconnection wiring or a separate metal layer. The invention overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract: A semiconductor component and a method for manufacturing the semiconductor component that mitigates electromigration and stress migration in a metallization system of the semiconductor component. A hardmask is formed over a dielectric layer and an opening is etched through the hardmask and into the dielectric layer. The opening is lined with a barrier layer and filled with an electrically conductive material. The electrically conductive material is planarized, where the planarization process stops on the barrier layer. Following planarization, the electrically conductive material is recessed using either an over-polishing process with highly selective copper slurry or a wet etching process to partially re-open the filled metal-filled trench or via. The recess process is performed such that the exposed portion of the electrically conductive material is below the dielectric layer.

Abstract: The invention provides an magnetic memory element having improved switching properties and zero field offset, and a manufacturing method thereof. The element comprises a first magnetic layer overlying a conductive layer and a nonmagnetic layer overlying the first magnetic layer. Next, a second magnetic layer is provided over the nonmagnetic layer, wherein the second magnetic layer comprises an antiferromagnetic layer overlying a ferromagnetic free layer to apply a small bias to the ferromagnetic free layer. Then, the first magnetic, nonmagnetic and second magnetic layers are patterned to form the memory element.

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths of 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is used to fabricate the interconnection circuits. A polymer base layer is formed on a glass carrier with an intermediate release layer. Alternate layers of metal and dielectric are formed on the base layer, and patterned to create an array of multi-layer interconnection circuits on the glass panel. A thick layer of polymer is deposited on the interconnection circuit, and openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings to form wells filled with solder.

Abstract: Disclosed is a method of fabricating a capacitor of a semiconductor device, which can produce an MIM capacitor in which an insulator film is formed to have a positive slope by means of a polymer, thereby preventing leakage of current in the capacitor. The method comprises the steps of: sequentially forming a first metal film, an insulator film, and a second metal film on a semiconductor substrate; patterning a second metal film to form an upper electrode; etching the insulator film using the upper electrode as a mask, and simultaneously forming a polymer at one side of the upper electrode; etching the insulator film which is not protected by the polymer, thereby removing the insulator film; and removing the polymer formed at said one side of the upper electrode.

Abstract: Semiconductor light-emitting devices are provided. The semiconductor light-emitting devices include a substrate and a crystal layer selectively grown thereon at least a portion of the crystal layer is oriented along a plane that slants to or diagonally intersect a principal plane of orientation associated with the substrate thereby for example, enhancing crystal properties, preventing threading dislocations, and facilitating device miniaturization and separation during manufacturing and use thereof.

Abstract: A method of monitoring and adjusting the position of a wafer with respect to an ion beam including setting the position of a wafer holder so that a wafer to be held therein is positioned at a tilt angle of 45 degrees and a twist angle of 45 degrees with respect to the path of an ion beam; positioning a n-type wafer without screen oxide in the wafer holder; implanting boron species into a region of the wafer at 160 KeV and a dose level of 5.0×1013 atoms/cm2; periodically measuring the sheet resistivity of a implanted wafer and readjusting the wafer tilt angle when the sheet resistivity is greater than 30 ohms/square.

Abstract: The present invention provides a method of manufacturing a semiconductor device, comprising the step of selectively grinding or polishing the peripheral portion and the beveled portion of a target substrate including a semiconductor substrate. The grinding or polishing of the target substrate is performed after the dry etching step for forming a trench in the target substrate, or after the depositing step of a copper layer providing a source of contamination of the process apparatus in forming a Cu-buried wiring. By grinding or polishing the peripheral portion and the beveled portion of the target substrate, the uneven portion in the peripheral portion and the beveled portion can be removed and copper is prevented from being exposed to the outside, thereby avoiding the particle generation and contamination of the process apparatus.

Abstract: A method and apparatus which provide one or more electromagnetic shield layers for integrated circuit chips containing electromagnetic circuit elements are disclosed. The shield layers may be in contact with the integrated circuit chip, including magnetic memory structures such as MRAMs, or in a flip-chip carrier, or both. A printed circuit board which supports the chip may also have one or more shield layers.