Abstract: A circuit element. In some embodiments, the circuit element includes a first terminal, a second terminal, and a layered structure. The layered structure may include a first conductive layer connected to the first terminal, a first piezoelectric layer on the first conductive layer, a second piezoelectric layer on the first piezoelectric layer, and a second conductive layer connected to the second terminal. The first piezoelectric layer may have a first piezoelectric tensor and a first permittivity tensor, and the second piezoelectric layer may have a second piezoelectric tensor and a second permittivity tensor, one or both of the second piezoelectric tensor and a second permittivity tensor differing, respectively, from the first piezoelectric tensor and the first permittivity tensor.

Abstract: Apparatus and method are provided. The apparatus includes at least one field effect transistor (FET), wherein the at least one FET comprises at least one gate overlaying at least one non-linear fin, wherein the non-linear fin is formed via modulating a mandrel by producing cut-outs in the mandrel via optical proximity correction (OPC). The method includes receiving a semiconductor wafer, forming source and drain areas for each of at least one FET on the semiconductor wafer; and forming at least one gate overlaying at least one non-linear fin in each of the at least one FET, wherein the non-linear fin is formed via modulating a mandrel by producing cut-outs in the mandrel via OPC.

Abstract: A light receiving device includes: a photoelectric conversion layer that includes a first compound semiconductor, and absorbs a wavelength in an infrared region to generate electrical charges; a plurality of contact layers that include a second compound semiconductor, and are provided on the photoelectric conversion layer at spacing intervals with respect to one another; and a covering layer that is formed to cover a portion corresponding to the spacing intervals of a front surface of the photoelectric conversion layer and side surfaces of the respective contact layers, and includes a Group IV semiconductor.

Abstract: A method of manufacturing semiconductor devices includes: forming source regions of a first conductivity type in a SiC-based semiconductor substrate, wherein dopants are introduced selectively through first segments of first mask openings in a first dopant mask and wherein a longitudinal axis of the first mask opening extends into a first horizontal direction; forming pinning regions of a complementary second conductivity type, wherein dopants are selectively introduced through second segments of the first mask openings and wherein the first and second segments alternate along the first horizontal direction; and forming body regions of the second conductivity type, wherein dopants are selectively introduced through second mask openings in a second dopant mask, wherein a width of the second mask openings along a second horizontal direction orthogonal to the first horizontal direction is greater than a width of the first mask openings.

Abstract: A method of manufacturing a semiconductor device including following steps is provided. A substrate is provided. An ion implantation process is performed on the substrate to form doped material layers at different depth positions of the substrate and to define at least one nanowire layer. The at least one nanowire layer and the doped material layers are alternately stacked. A patterning process is performed on the at least one nanowire layer and the doped material layers to form at least one nanowire and doped layers. The at least one nanowire and the doped layers are alternately stacked to form a stack structure. A dummy gate structure spanning over the stack structure is formed. Spacers located on sidewalls of the dummy gate structure is formed. The dummy gate structure is removed to expose the at least one nanowire and the doped layers. The exposed doped layers are removed to form openings.

Abstract: A flexible circuit board, a display device and a method for mounting a flexible circuit board are disclosed. The flexible circuit board includes: a bendable portion, the flexible circuit board being bendable at the bendable portion to go into a bent state so as to be connected to a workpiece; and at least one opening in the bendable portion. In response to the bent state, a gap is formed between the bendable portion and the workpiece, and the at least one opening is in communication with the gap.

Abstract: After a dummy control gate electrode and a memory gate electrode are formed and an interlayer insulating film is formed so as to cover the gate electrodes, the interlayer insulating film is polished to expose the dummy control gate electrode and the memory gate electrode. Thereafter, the dummy control gate electrode is removed by etching, and then a control gate electrode is formed in a trench which is a region from which the dummy control gate electrode has been removed. The dummy control gate electrode is made of a non-doped or n type silicon film, and the memory gate electrode is made of a p type silicon film. In the process of removing the dummy control gate electrode, the dummy control gate electrode is removed by performing etching under the condition that the memory gate electrode is less likely to be etched compared with the dummy control gate electrode, in the state where the dummy control gate electrode and the memory gate electrode are exposed.

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a bottom electrode that is disposed over a lower interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A data storage structure is arranged over the bottom electrode and a multi-layer top electrode is disposed over the data storage structure. The multi-layer top electrode includes conductive top electrode layers separated by an oxygen barrier structure that is configured to mitigate movement of oxygen between the conductive top electrode layers. A sidewall spacer is disposed directly over the bottom electrode and has a sidewall that covers outermost sidewalls of the conductive top electrode layers and the oxygen barrier structure.

Abstract: Provided are nanocrystalline graphene and a method of forming the nanocrystalline graphene through a plasma enhanced chemical vapor deposition process. The nanocrystalline graphene may have a ratio of carbon having an sp2 bonding structure to total carbon within the range of about 50% to 99%. In addition, the nanocrystalline graphene may include crystals having a size of about 0.5 nm to about 100 nm.

Abstract: A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.

Abstract: In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

Abstract: A light emitting assembly comprising a solid state device, when and if coupleable with a power supply constructed and arranged to power the solid state device to emit from the solid state device a first wavelength radiation, and an enveloping vessel enhancing the luminescence of the solid-state device and providing a mechanism for arranging luminophoric medium in receiving relationship to said first, radiation, and which in exposure to said first radiation, is excited to responsively emit second wavelength radiation or to otherwise transfer its energy without radiation to a third radiative component. In a specific embodiment, monochromatic blue or UV light output from a light-emitting diode is converted to achromatic light without hue by packaging the diode with fluorescent organic and/or inorganic fluorescers and phosphors on the walls of the solid-state light envelope which keeps the diode and the fluorescers and phosphors under a vacuum or a rare or Noble gas.

Abstract: A method for making a semiconductor structure includes defining one or more device areas and one or more interconnect areas on a silicon substrate, forming trenches in the interconnect areas of the silicon substrate, oxidizing the silicon substrate in the trenches to form silicon dioxide regions, forming a III-nitride material layer on the surface of the silicon substrate, forming devices in the device areas of the gallium nitride layer, and forming interconnects in the interconnect areas. The silicon dioxide regions reduce parasitic capacitance between the interconnects and ground.

Abstract: A display panel includes a substrate, a thin film transistor (TFT) layer on the substrate, and multiple connection lines disposed between the substrate and the TFT layer. The TFT layer includes TFTs and signal lines connected to the TFTs for providing signals to the TFTs. Each connection line is electrically connected to a signal line. The present invention also teaches a display panel manufacturing method. The present invention has the connection lines formed in the display area, instead of in the non-display area, thereby reducing the width of the non-display area.

Abstract: A hermetically sealed component may comprise a glass substrate, a device with at least one electrical port associated with the glass substrate, and a glass cap. The glass cap may have at least one side wall. The glass cap may have a shaped void extending therethrough, from top surface of the glass cap to bottom surface of glass pillar. An electrically conductive plug may be disposed within the void, the plug configured to hermetically seal the void. The electrically conductive plug may be electrically coupled to the electrical port. The glass cap may be disposed on the glass substrate, with the at least one side wall disposed therebetween, to form a cavity encompassing the device. The side wall may contact the glass substrate and the glass cap to provide a hermetic seal, such that a first environment within the cavity is isolated from a second environment external to the cavity.

Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises DRAM having bit-cells. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. In one example, the second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights. Ultra high-bandwidth is changed by placing the first die below the second die. The two dies are wafer-to-wafer bonded or coupled via micro-bumps.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate and a first crack-detecting structure positioned in the substrate and comprising a first capacitor unit. The first capacitor unit comprises a first bottom conductive layer positioned in the substrate, a first capacitor insulating layer surrounding the first bottom conductive layer, and a first buried plate surrounding the first capacitor insulating layer.

Abstract: A semiconductor chip including an alignment pattern is provided. The semiconductor chip includes a substrate associated with a main chip region of a semiconductor wafer and including a scribe lane. A lower interlayer insulating layer is disposed on the substrate, a low-K layer including dummy metal patterns is disposed on the lower interlayer insulating layer, an alignment pattern is disposed on the low-K layer, and a passivation layer covers the alignment pattern.

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.