Abstract: A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.

Abstract: An FEC coder in a transmission device according to an exemplary embodiment of the present disclosure performs BCH coding and LDPC coding based on whether a code length of the LDPC coding is a 16 k mode or a 64 k mode. A mapper performs mapping in an I-Q coordinate to perform conversion into an FEC block, and outputs pieces of mapping data (cells). The mapper defines different non-uniform mapping patterns with respect to different code lengths even an identical coding rate is used by the FEC coder. This configuration improves a shaping gain for different error correction code lengths in a transmission technology in which modulation of the non-uniform mapping pattern is used.

Abstract: A data error correction circuit and a data transmission circuit are disclosed. The data error correction circuit includes: a decoding circuit having an input terminal connected to a data bus, and configured to receive first data and a check code of the first data and output an error correction code of the first data based on the check code; and an error correction latch module having a first input terminal connected to the data bus and a second input terminal connected to an output terminal of the decoding circuit, and configured to latch the first data corresponding to the error correction code and generate and output second data according to the error correction code and the corresponding first data.

Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customer's system using the device. Additional embodiments are also provided and described in the disclosure.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication device may identify a first set of bits associated with a first set of modulation layers. The wireless communication device may interleave a second set of bits associated with a second set of modulation layers to obtain an interleaved second set of bits. The wireless communication device may generate a combined set of bits based at least in part on combining the second set of bits and at least a portion of the first set of bits. The wireless communication device may perform a transmission based at least in part on the combined set of bits and the second set of bits. Numerous other aspects are described.

Abstract: Various embodiments and implementations of graph-neural-network (GNN)-based decoding applications are disclosed. The GNN-based decoding schemes are broadly applicable to different coding schemes, and capable of operating on both binary and non-binary codewords, in different implementations. Advantageously, the inventive GNN-based decoding is scalable, even with arbitrary block lengths, and not subject to typical limits with respect to dimensionality. Decoding performance of the inventive GNN-based techniques demonstrably matches or outpaces BCH and LDPC (both regular and 5G NR) decoding algorithms, while exhibiting improvements with respect to number of iterations required and scalability of the GNN-based approach. These inventive concepts are implemented, according to various embodiments, as methods, systems, and computer program products.

Abstract: This application relates to a method for analyzing crosstalk between qubits, performed by a terminal. The method includes identifying a first qubit and a second qubit; performing spectral quantum process tomography on quantum states corresponding to the first qubit and the second qubit, to obtain a first eigenspectrum of a signal function corresponding to the first qubit and a second eigenspectrum of a signal function corresponding to the second qubit; performing spectral quantum process tomography on the quantum states corresponding to the first qubit and the second qubit, to obtain a third eigenspectrum of a common signal function of the first qubit and the second qubit; and determining a crosstalk intensity between the first qubit and the second qubit based on the first eigenspectrum, the second eigenspectrum, and the third eigenspectrum.

Abstract: A method for processing data stored in a memory unit. The method includes the following steps: ascertaining a randomly or pseudo-randomly formed test pattern, which characterizes at least one first subarea of a memory area of the memory unit, forming, as a function of the test pattern, a test variable associated with data stored in the at least one first subarea.

Abstract: Techniques regarding quantum computer error mitigation are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an error mitigation component that interpolates a gate parameter associated with a target stretch factor from a reference model that includes reference gate parameters for a quantum gate calibrated at a plurality of reference stretch factors.

Abstract: A quantum system controller configured to perform (near) real-time quantum error correction is provided. The controller comprises a processing device comprising at least one first processing element; a time-indexed command (TIC) sequencer comprising at least one second processing element; and a plurality of driver controller elements configured to control the operation of respective components and associated with respective buffers and processing elements. The processing device is configured to generate commands and the TIC sequencer is configured to cause the time-indexed execution of the commands by the appropriate driver controller elements.

Abstract: A flit-based packetization approach is used for transmitting information between electronic components. A protocol stack can generate transaction layer packets from information received from a transmitting device, assemble the transaction layer packets into one or more flits, and protect the flits with a flit-level cyclic redundancy check (CRC) scheme and a flit-level forward error correction or parallel-forward error correction (FEC) scheme. Flit-level FEC schemes can provide improved latencies and efficiencies over per-lane FEC schemes. To improve retry probability, flits can contain information indicating whether immediately preceding flits are null flits. Receivers can avoid sending a retry request for a corrupted flit if a seceding flit indicates the corrupted flit is a null fit. Parity flits can be used to protect groups of flits and correct single-flit errors.

Abstract: A storage device includes a memory including a plurality of regions arranged along a first axis and a second axis orthogonal to each other, each of the plurality of regions belonging to one of first groups and one of second groups; and a controller configured to, when a programmed and weak region exists, put into a scan list on the basis of a weak list, a programmed and weak sub-region included in the programmed and weak region among the plurality of regions, put into the scan list, a first programmed and adjacent sub-region in a first programmed and adjacent region selected according to a second axis expansion order among the plurality of regions, and put into the scan list, a second programmed and adjacent sub-region in a second programmed and adjacent region selected according to a first axis expansion order among the plurality of regions.

Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.

Abstract: In some examples, a computing device includes a first reset domain including a test controller and a configurable test logic. The computing device includes a second reset domain including a subsystem to be measured by the configurable test logic. The first reset domain is to enter a reset mode, and after exiting the reset mode, receive configuration information that configures the configurable test logic. The test controller of the first reset domain is to maintain the second reset domain in a reset mode after the first reset domain has exited the reset mode of the first reset domain, and responsive to the received configuration information for configuring the configurable test logic, provide a reset release indication to the second reset domain to allow the second reset domain to exit the reset mode of the second reset domain.

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.

Abstract: Method, systems and apparatuses may provide for technology that executes a margin test of a first memory storage based on a subset of first signals associated with the first memory storage. The technology determines, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints. The technology determines, based on the first margin data, whether to execute a signal training process.

Abstract: Systems, apparatus and methods are provided for temperature assisted non-volatile storage device management in a non-volatile storage system. In one embodiment, a non-volatile storage system may comprise a temperature sensor, a non-volatile storage device and a processor. The processor may be configured to obtain a read-out from the temperature sensor, generate a predicted real-time on-die temperature for the non-volatile storage device based on the read-out, generate an estimated threshold voltage for reading data stored in the non-volatile storage device based on the predicted real-time on-die temperature and conduct a local sweep of a reference voltage using the estimated threshold voltage as a starting point to obtain a final read reference voltage with a minimum read bit error rate.

Abstract: A redundant circuit assigning method a includes: first test item is executed and first test data is acquired; a first redundant circuit assigning result including the number of assigned local redundant circuits and position data of the assigned local redundant circuits is determined according to the first test data; a second test item is executed and second test data is acquired; when fail bits acquired during execution of the second test item include one or more fail bits beyond the repair range of the assigned local redundant circuits and assigned global redundant circuits, and the assignable redundant circuits have been assigned out, target position data of fail bits in a target subdomain and a related subdomain is acquired based on the first test data and the second test data; and a second redundant circuit assigning result is determined according to the first test data and the second test data.

Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

Abstract: The examples disclosed herein provide classifying quantum errors. In particular, a classical computing system receives quantum error data from a first quantum computing device of a quantum computing system. The quantum error data includes error identification data and error correction data. The error identification data is associated with occurrence of a quantum error. The error correction data is associated with a corrective action taken by the first quantum computing device to correct the quantum error. The classical computing system determines an error type of the quantum error of the error identification data. The classical computing system associates an error classification tag with the quantum error data. The error classification tag identifies a quantum error type. The classical computing system sends the error classification tag to the first quantum computing device. The classical computing system processes a quantum computing request based on the error classification tag.