Abstract: The present invention consists of an apparatus comprising a phase locked loop and a frequency loop having a discriminator and a disable. The disable is used to electrically disconnect the frequency loop from the phase locked loop when the phase of the output from the voltage controlled oscillator is within a preset range of the incoming signal. The disable acts to provide an adjusting voltage signal, set by the discriminator, to the phase locked loop when the output and input signal phases are out of the preset range. When they are within the preset range the disable outputs a zero voltage regardless of the input from the discriminator.

Abstract: An oscillator-mixer arrangement including a dual-gate field effect transistor of the Schottky type for supplying an intermediate frequency output signal. The output signal is obtained by subtractively mixing a high frequency input signal and a signal produced in the arrangement. The input signal is applied to the first gate electrode (G.sub.1), the produced signal is controlled by the second gate electrode (G.sub.2), and the output signal is recovered at the drain electrode (D), while the source electrode (S) is directly connected to ground. A micro-strip line having a characteristic impedance Z.sub.O which is electromagnetically coupled to a dielectric resonator and loaded by an impedance (Z.sub.O) is connected to the second gate electrode (G.sub.2). The arrangement is intended to be included in a receiver front end assembly for very high frequency waves, typically of a frequency of 12 GHz, used for broadcasting radio-television programs by artificial satellites.

Abstract: An inverter (100) receives a DC voltage and generates therefrom a square wave output signal. The inverter includes an output transformer (T3) and a saturable core transformer (T4). The saturable core transformer (T4) provides base current for a first transistor (Q3) and a second transistor (Q4). The first transistor (Q3) and the second transistor (Q4) alternatively turn on and off, causing a square wave to appear across the secondary winding of the output transformer (T3). The primary winding of the output transformer is coupled to the collectors of the first and second transistors via a pair of windings (L10, L11) magnetically coupled to the saturable transformer (T4). A pair of diodes (D4, D5) are provided to prevent the output leads of primary windings of the output transformer (T3) from dropping below ground potential.

Abstract: A reference signal from a reference signal source is supplied to a frequency transformer and a side band signal generator. The frequency transformer is formed mainly by up-converters and produces a frequency m times as high as the frequency f.sub.s of the reference signal. The side band signal generator outputs signals of base and harmonic frequencies f.sub.s, 2f.sub.s, 3f.sub.s, . . . and nf.sub.s (where n is less than m) and produces less phase noise than does the frequency transformer. The outputs of the frequency transformer and the side band signal generator are frequency mixed by a frequency mixer, and one frequency component in the frequency-mixed output is selected by a variable filter.

Abstract: A synchronization circuit for a free-running oscillator, in which a multi-tapped delay line provides delayed outputs incrementally spaced throughout the period and at the same frequency as the oscillator. That delayed signal closest in time to a reference signal is selected as the output signal, synchronized to the reference signal.

Abstract: An oscillator comprises an amplifier with a feedback loop from the output to the input thereof, the feedback loop including a resonator such as a crystal providing oscillation of the amplifier at a predetermined frequency. A balanced modulator coupled to the amplifier generates a voltage varying at the same frequency, said voltage being selectably variable in amplitude from zero upward either in phase with the amplifier or 180 degrees out of phase therewith. The voltage is selectably inserted into the feedback loop 90 degrees out of phase with the output of the amplifier, whereby, when it is inserted, the frequency of oscillation of the amplifier varies from the predetermined frequency in direction depending upon the phase relationship of the amplifier and voltage and in amount upon the amplitude of the voltage.

Abstract: A temperature stabilizing circuit for a microwave oscillator employing a field effect transistor on an AsGa substrate, in which a temperature-stabilized frequency is obtained by varying the gate-channel capacitance of an FET included in the oscillator resonance circuit. The capacitance is controlled by a voltage derived from a voltage divider comprising a series arrangement of several Schottky diodes or FET's. The circuit is suited to assembly as an integrated monolithic circuit comprising FETs on a AsGa substrate, for micro wave frequency applications such as for example, processing 12 GHz satellite television signals.

Abstract: A clock pulse generator system for providing a highly stable clock signal consists of two separate redundant clock signal generators which are controlled to operate in dead synchronization with each other. A microprocessor controlled digital phase lock loop operates to control each of the two clock signal generators and selects among a plurality of operating states such that the average dynamic phase difference in the two clock pulse signals generated is practically zero. Furthermore, the instantaneous dynamic phase difference does not exceed the phase noise of the voltage controlled crystal oscillators of the phase lock loops and, in one embodiment, is normally less than ten pico seconds, each phase lock loop comprising means for performing a fine, as well as coarse, phase comparison among internally or externally generated reference signals, only one of which is the highly stable clock signal output.

Abstract: A phase lock loop circuit comprises a variable frequency oscillator having a control input and an output, a divider having an input coupled with the output of the oscillator and an output coupled with the first input of a phase or frequency comparator. The comparator has a second input for a reference frequency (F.sub.REF) and an output coupled with the oscillator control input for providing a signal which is related to the difference in phase or frequency of the signals at the first and second inputs to effect phase locking of the oscillator to the reference signal. A detector provides a switching signal when the control signal falls outside a predetermined range and a switch in the phase lock loop is responsive to the switching signal to open the loop.

Abstract: An evacuated wall-coated sealed alkali atom cell for an atomic frequency standard, including a cell bulb having an inner wall subjected to cleaning by means of a bakeout step and a r.f. scrubbing step under vacuum, whereupon the inner wall is provided with a deuterated paraffin coating. An alkali atom .sup.87 Rb and/or .sup.85 Rb, and/or .sup.133 Cs is sealed in the cell bulb under vacuum.

Abstract: A voltage controlled oscillator comprises a tank circuit for determining an oscillation frequency, a first circuit for delaying the signal having the oscillation frequency, a second circuit for advancing the signal having the oscillation frequency, the first and second circuit being connected in series, a third circuit interposed between the tank circuit and the series connection of the first and second circuits, the third circuit having the same equivalent circuit of the series connection, a first gain controlled amplifier amplifying the output from the first circuit, a second gain controlled amplifier amplifying the output from the second circuit, an adder for adding outputs from the first and second gain controlled amplifiers, a control circuit controlling the gains of the first and second gain controlled amplifiers, and a feed-back circuit for feeding the output of the adder to the tank circuit.

Abstract: A temperature and voltage stable clock circuit for use in implantable cardiac pacers employs CMOS devices to minimize current drain. The circuit includes a timing capacitor which is alternately charged to and discharged between two established threshold voltages during respective charge and discharge cycles, the periods of which determine the clock frequency. To render the frequency of the clock circuit independent of changes in capacitor charge and discharge currents brought about by changes in temperature, the threshold voltage is increased with temperature so that the charge and discharge cycles remain constant. To render the frequency of the clock circuit independent of changes in the power supply voltage, a Wilson current source is used to maintain a constant charge and discharge current to the timing capacitor.

Abstract: A low power, wide bandwidth oscillator capable of oscillating at frequencies of greater than 350 MHz and capable of being implemented in relatively few parts is disclosed. A switching section controls the resonant frequency of a resonator and is connected in DC series with an amplifier. A regulator-buffer section simultaneously serves as a voltage regulator and RF signal buffer.

Abstract: An oscillation circuit includes as its principal components a Clapp capacitor and two feedback capacitors connected to each other and a resonance coil. A first series circuit including a first variable-capacitance diode and a first DC cutoff capacitor is connected in parallel with the resonance coil, while a second series circuit including a second variable-capacitance diode and a second DC cutoff capacitor is connected to a first diode such that a certain polarity terminal of the second variable-capacitance is faced against the same polarity terminal of the first diode. One end of the second DC cutoff capacitor in the second series circuit is connected to the one of the feedback capacitors. Furthermore, means is provided at the joint of the first variable-capacitance diode and the first DC cutoff capacitor for applying a DC voltage to enable the first and second variable-capacitance diodes.

Abstract: A switching circuit apparatus driven by a relatively low DC power supply voltage, which includes a power supply terminal designed to receive a DC power source voltage, a pair of switching circuits comprising switching transistors (28, 30 and 32, 34) connected in parallel with each other and connected to the power supply terminal, first circuit means (10,12) connected for supplying the respective switching circuits with a switched signal, and a second circuit means (16, 18, 40, 14) connected for supplying the respective switching circuits with a pair of control signals which are opposite in phase and which are never both at a potential difference other than a prescribed potential at the same time. The switching circuit transistors (28, 30 or 32, 34) are all fully conductive prior to any transition in which two are rendered non-conductive by the control signals, thereby enable operation of the circuit with low power consumption.

Abstract: A phase locked loop circuit (16) includes means to eliminate harmonic frequency locking. The phase locked loop includes a voltage controlled oscillator (1) which provides an output signal (V.sub.out) which is compared with the input signal (V.sub.in) by a phase detector (4). The output signal from the phase detector is integrated and the output signal of the integrator (7) is placed on the control input lead of the voltage controlled oscillator. The output signal of the voltage controlled oscillator is provided to a frequency detector (14, 17) which determines if the output frequency is within a predefined range. If the output frequency is above the predetermined range, a limiter circuit (15) provides a low voltage output signal to the control input lead of the VCO in order to pull the input voltage of the VCO to a voltage which corresponds with the appropriate operating range of the phase locked loop.

Abstract: A microwave solid-state oscillator includes a casing hermetically enclosing a microwave oscillation device and a dielectric resonator electromagnetically coupled with the microwave oscillation device, an output terminal leading out an oscillation output from said casing, and a microwave terminal electromagnetically coupled to the dielectric resonator, one end of which is connected to a microwave line having a terminating admittance at the outside of the casing.

Abstract: A low current oscillator/buffer amplifier configuration is disclosed which provides a simple, inexpensive, low power oscillator with reduced harmonic output. Buffer 60 is coupled to the resonant tank circuit 58 of oscillator 50 by means of impedance transform network 70. This technique of tapping directly from the tank provides a buffered output signal having low harmonic content. Furthermore, impedance transform network 70 permits coupling feedback amplifier 52 to buffer amplifier 62 in a totem-pole amplifier stage configuration. This feature provides a significant current savings over conventional oscillator/buffer circuits. The instant invention is particularly well adapted for use as reference frequency oscillators in portable radio applications.

Abstract: An analog phase interpolator for use in Fractional-N frequency synthesis is disclosed. The interpolator employs a precision gating circuit adapted to generate analog signals indicative of a precisely determined time interval. The signals switch a precision correction current to precisely compensate for the phase detector "beat note" to reduce the magnitude of FM spurious signals. The time interval is inversely proportional to the synthesizer output frequency and the gating circuit automatically compensates for changes in the output frequency. The precision gating circuit includes a prescaler circuit for prescaling the output signal frequency to provide a clock signal, and is responsive to an "initiate" pulse to provide two pulses delayed by a predetermined number of clock signal periods. A very high degree of time integrity exists in the relation of the edges of the two pulses.

Abstract: A phase modulator includes a digital frequency word generator, an adder and a register arranged to generate recurrent digital sawtooth signals at a carrier rate. A second digital adder is coupled to receive the sawtooth signals and also receives digital information signals. The adder produces recurrent digital sawtooth signals phase-modulated by the information signal. A pair of adders receive the digital sawtooth signals and mutually sign-reversed digital information signals to produce a pair of oppositely phase-modulated constant-amplitude signals in a pair of channels. A sine memory is addressed by the phase-modulated digital sawtooth signals to produce phase-modulated sinusoidal-representative digital signals. The digital signals are then converted to analog signals. Since the two channels contain signals which are phase-modulated but not amplitude-modulated, the signals may be amplified by nonlinear amplifiers.