Abstract: A microprocessor for performing an interrupt operation receives an interrupt-enable signal representative of occurrence of at least interrupt request and interrupt level information representative of a selected one of interrupt sources issuing the interrupt request and includes an interrupt receiving unit activated by the interrupt-enable signal for producing vector fetching command information when an interrupt operation responsive to the interrupt level information is acceptable, an interrupt vector generation unit activated by the interrupt-enable signal for generating interrupt vector information, and an execution unit fetching the interrupt vector information in response to the vector fetching command information, the execution unit thereby initiates an interrupt operation by use of the interrupt vector information and returning interrupt acknowledge information as a part of the interrupt operation.

Abstract: An arrangement for transmitting information from a first component of a computer system to a second component of the computer system including a source channel associated with the first component of the computer system; a destination channel associated with the second component of the computer system; apparatus for interconnecting the source and the destination channels; the source channel including apparatus for creating a stream of information in a prescribed format, apparatus for designating a destination channel as an address for the stream of information, and apparatus for transferring the stream of information to the apparatus for interconnecting the source and the destination channels; and the destination channel including apparatus for receiving a stream of information in the prescribed format from the apparatus for interconnecting the source and the destination channels, apparatus for receiving control signals apart from the stream of information, and apparatus for controlling the use of the stream o

Abstract: A data processor being provided with a data register having a double width of the width of a general purpose register for inputting/outputting data with respect to the operand access unit, and a data transfer path which is composed of a plurality of buses between the register file and the data register and which simultaneously transfers two data, in which, in the case where an LDCTX instruction which is the instruction for loading data to more than two register is executed, a combined data of two data each of which is to be loaded in different register is transferred from the operand access unit to the data register, and high order 4 bytes of data and low order 4 bytes of in the data register are simultaneously transfers to two register through two data transfer paths, respectively, and in the case where an STCTX instruction which is the instruction for storing data from more than two register is executed, contents of the two registers are simultaneously transferred to a high order 4 bytes and a low order 4 b

Abstract: A data buffer that compensates the differences in data rates, between a storage device and an image compression processor. A method and apparatus for the real time indexing of frames in a video data sequence.

Abstract: A computer interconnect including a plurality of nodes, each node capable of joining to a component of a computer, each node including apparatus for transferring signals between the component and the node, apparatus for storing packets of data, apparatus for signalling each other node that a packet of data exists for transfer to a component associated with that node, apparatus for sensing signals from another node indicating that a packet of data exists for transfer to a component associated with that node, and apparatus for transferring packets of data stored at one node to the apparatus for transferring signals between the component and the node of another node.

Abstract: A system, method and program for adjusting a resource reservation for multimedia and normal traffic. An initialization file is used for storing data concerning a resource including a current maximum resource reservation for multimedia traffic. The user is presented the current maximum resource reservation, preferably in a graphical user interface to allow the user to adjust the resource reservation to a new maximum resource reservation in the initialization file. One preferred graphical user interface presents a range of resource reservations is represented as a scale and the current maximum resource reservation as a point on the scale. The resource reservation is used by the operating system or other software for reserving a portion of the resource. The remainder of the resource is allocated to normal traffic.

Abstract: A system for securing communications between devices connected to a ring network. In accordance with the present invention, when a message frame is passed around the ring network, a gate keeper circuit associated with at least one port of a hub determines whether the message frame is intended for any of the nodes connected to that port. If the message frame is not intended for any of the nodes connected to that port, the message frame is encoded before it exits the hub through the port to traverse the subnetwork connected to the port, and decoded after it reenters the hub through the port. If and only if at least one node on the subnetwork connected to the port is intended to receive the message frame, then each node connected to that port can read the message frame.

Abstract: A data processing system for regulating access to a communication network is disclosed herein. The data processing system employs a component that can be implemented in hardware logic or software. The component regulates access to the priority queue or transmit channel that is attached to the shared medium local area network section. All access to the priority queue or transmit channel must pass through this component, thus subjecting all communication transactions to rejection or tracking by the component. The component allocates a frame size based on the information to be transmitted and the priority to assure the transmission will be completed in line with the quality of service required. The component monitors the rate and size of messages to assure that an application's actual throughput does not exceed its negotiated throughput. The component, moreover, is capable of operating in correction mode where throughput and frame size violations are prevented and reported.

Abstract: A computer forms a node in a network, consisting of computer nodes linked together into a minimum spanning tree topology. When a computer receives a message from a first node linked to it, it forwards the message to other nodes linked to that computer, as well as storing information about the message. As replies are received from the other computers, they are stored and collated together, to allow the computer to send just a single reply message back to the originating node based on the collated replies. This single reply is in turn collated at the next node. The message requests deletion of a particular node from the network. No node deletes the node from the network until replies have been received from all the nodes to which the message was forwarded.

Abstract: A stereo computer system with resources to produce and record surround sound channels. Such surround sound channels are played or recorded using an audio card added to the computer system, which audio card controls additional speakers and/or microphones. Software for redirecting instructions from existing stereo application programs and sending these instructions to the existing audio device driver and the additional audio device driver is provided. Resources for processing the digital audio data for either extracting surround sound channels from two channel data provided by the application, or for encoding two sets of two channel audio data recorded by the two audio cards is also included.

Abstract: A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme.

Abstract: A peripheral device for use with a data processing apparatus. The apparatus has a peripheral port with a set of terminal pins consisting of first to ninth pins disposed in a row. The first pin is assigned for one of a power source and the ground potential, the ninth pin for the other of the power source and the ground potential, the second, third, seventh and eighth pins for transmitting data signals, and the fourth to sixth pins for transmitting control signals. The apparatus has an element for selecting the communication mode of the peripheral device connected to the peripheral port, based on the data signals transmitted from the second, third, seventh and eighth pins.

Abstract: A computer network system includes a plurality of computers and a network connected to the computers for allowing them to interchange data. Each computer has a data send module and a data receive module. The data send module is made up of a means for sending a data frame to the network in response to a send request, a resend number storing means for storing the number of times that the data frame is to be resent, and a means for updating the content of the resend number storing means upon receiving a frame for changing the number of times that the data frame is to be resent from the network. The data receive module includes a receive buffer for storing the data frame received from the network, and a means for sending, when the receive buffer is full, the frame for changing the number of times that the data frame is to be resent to the network.

Abstract: A computer system has both positive decode agents and subtractive decode agents that are targets of bus transactions, as well as an agent that does not perform a positive decode of a bus transaction, yet does claim bus transactions on behalf of agents to whom a bus transaction is directed.

Abstract: A multi-processor system that supports multiple programmable interrupt controllers (PIC). An advanced programmable interrupt controller (APIC) provides interface between the processors and the PICs. The APIC provides interface between processors and other I/O devices also. The APIC sends an interrupt request data packet with a first field set to a processor identification number, a second field set to a type of the device that sent interrupt request and a third field. The third field is set to an interrupt vector if the device sending the interrupt request to the APIC is a device other than PIC. The third field is set to a predetermined identification number of the PIC if the interrupt request is from the PIC. A processor, to which the interrupt is directed to, receives the packet. If the interrupt request is from a PIC, the processor uses the third field to identify which of the multiple PICs caused the interrupt.

Abstract: A multimedia collaboration system that integrates separate real-time and asynchronous networks--the former for real-time audio and video, and the latter for control signals and textual, graphical and other data--in a manner that is interoperable across different computer and network operating system platforms and which closely approximates the experience of face-to-face collaboration, while liberating the participants from the limitations of time and distance. These capabilities are achieved by exploiting a variety of hardware, software and networking technologies in a manner that preserves the quality and integrity of audio/video/data and other multimedia information, even after wide area transmission, and at a significantly reduced networking cost as compared to what would be required by presently known approaches. The system architecture is readily scalable to the largest enterprise network environments.

Abstract: In a distributed file system having a plurality of file servers each associated with a plurality of workstations having cache memories, data locks granted by the file servers to the workstations have variable lock lifetimes that are selected based on system parameters. The parameters selected to determine lock lifetimes can be either statically determined, in which case system operating parameters such as read/write ratio for data objects are assumed, or can be dynamically determined, in which case real-time system operating parameters such as current read/write ratios are used to determine the appropriate lock lifetime.

Abstract: Apparatus for monitoring and displaying the status of a local area network. The network includes a hub with ports for connection to various data terminal equipment in a star configuration and for connection to other hubs of the network. The hubs each have different types of plug-in modules which have ports for connecting the hub to different types of network cable such as fiber optic cable, unshielded twisted pair cable and shielded twisted pair cable. Information is automatically provided to a control console identifying the types of modules and the location of the modules in the hub so that an image of the actual hub can be displayed on the screen of the control console. The actual hub image shows the location and types of modules installed in the hub. In addition, information regarding the connection of each of the hubs to other hubs of the network is obtained and provided to the control console.

Abstract: A switch controlling device for a serial communication port and a light communication port having an asynchronous communication part, a switch, a micro-controller, multiplexers, an EIA driver, and a light signal input/output part. The switch controlling device for the serial communication port and the light communication port is driven by a user selecting the serial communication port or the light communication port, after both the serial communication port and light communication port have been installed in a computer system.

Abstract: Method and apparatus for buffering data packets in a data communication controller environment. In general, the communication controller is interfaceable with a host processor and includes a control unit for accessing a communication medium. Each data packet to be transmitted or received is assigned a unique packet number. Packet number assignment is carried out by a memory management unit which dynamically allocates to each assigned packet number, one or more pages in data packet buffer memory for the storage of the corresponding data packet. If requested storage space is unavailable at the time of request, the memory management unit will allocate a page or pages to an available packet number as the pages become free. Upon issuing the assigned packet number, the physical addresses of the allocated pages of buffer memory storage space are generated in a manner transparent to both the host processor and the control unit.