Abstract: A method of correcting alignment with high alignment precision is provided. A mean value of true shears of the past (true shears for data numbers i=1 to 4) is determined. A difference (VA1) between the immediately preceding true shear (for the data number i=1) and the two-cycle previous true shear (for the data number i=2) is calculated. The product (VA2) of the true shear difference (VA1) and a constant value is calculated. Adding the product (VA2) to the mean value to determine a predicted stepper correction value (Pr1). A stepper set value is determined based on the predicted stepper correction value (Pr1).

Abstract: A method of underfilling a space between a semiconductor flip chip and a substrate to encapsulate a plurality of electrical connections with a viscous underfill material. The flip chip is mounted to the substrate with a plurality of electrical connections thereby forming a gap between opposed surfaces of the flip chip and substrate. The viscous underfill material is dispensed adjacent at least one edge of the flip chip. The flip chip and substrate are the rotated to move the underfill material into the gap under the influence of centrifugal force. The underfill material is cured after fully encapsulating the electrical connections.

Abstract: A method for fabricating a contact of a semiconductor device is disclosed, which efficiently removes an etching damage layer and residual layers when forming a contact of a semiconductor memory device, thereby improving a motion characteristic of the device. The method for fabricating a contact of a semiconductor device includes the steps of forming an insulating layer on a semiconductor substrate, forming a contact hole by selectively etching the insulating layer, so that a surface of the semiconductor substrate is exposed, primarily removing reaction by-products as well as a plasma damage layer at a bottom surface of a contact hole, with a pressure higher than that during the formation of the contact hole, and with a plasma source power and a bias power lower than those during the formation of the contact hole, and secondarily removing a residual plasma damage layer remaining after the primary removing, by an anisotropic etching with a light etching process.

Abstract: A method for improving the quality of metal conductor tracks on semiconductor structures of wafers, includes covering each metallizing plane, after being deposited and structured, by an interlevel dielectric. An integrated annealing or tempering is performed at the beginning of the deposition of the interlevel dielectric. The quality of metal conductor tracks on semiconductor structures is improved by preventing the recreation of voids and a considerable shortening of the process time is achieved.

Abstract: The present invention provides a method for fabricating an integrated circuit (IC) structure having an Al contact in electrical communication with Cu wiring embedded in the initial semiconductor wafer. In accordance with the method of the present invention, the Al contact is formed in areas of the IC structure which contain or do not contain an underlying region of Cu wiring. The present invention also provides a method of interconnecting the fabricated structure to a semiconducting packaging material through the use of a wirebond or Controlled Collapse Chip Connection (C4) solder.

Abstract: A method of fabricating trenches has been achieved. The method may be applied to damascene and dual damascene contacts to prevent damage to organic low dielectric constant materials due to photoresist ashing. A semiconductor substrate is provided. A first dielectric layer is deposited overlying the semiconductor substrate. A first etch stopping layer is deposited overlying the first dielectric layer. A second etch stopping layer is deposited overlying the first etch stopping layer. An optional anti-reflective coating is applied. A photoresist layer is deposited. The photoresist layer is patterned to define openings for planned trenches. The second etch stopping layer is etched through to form a hard mask for the planned trenches. The photoresist layer is stripped away by ashing where the first etch stopping layer protects the first dielectric layer from damage due to the presence of oxygen radicals.

Abstract: An interconnect for BGA packages, a BGA package fabricated using the interconnect, and a method for fabricating BGA packages using the interconnect, are provided. The interconnect includes multiple polymer substrates on which patterns of conductors are formed. Each substrate can be used to fabricate a BGA package. The conductors on the substrates include end portions having bonding vias formed therethrough in alignment with access openings in the substrates. During fabrication of the BGA packages, the bonding vias allow the conductors to be bonded to bond pads on semiconductor dice by forming metal bumps on the bonding vias and bond pads. The access openings in the substrates provide access to the bonding vias and bond pads for a bonding tool configured to form the metal bumps. In addition to the bonding vias, the conductors include ball bonding pads configured for attaching ball contacts, such as solder balls, to the conductors and substrates.

Abstract: The structure of high-Q inductor applied in a monolithic circuit according to the invention comprises a plurality of spiral metal lines and a plurality of dielectric layers, each dielectric layer formed between two adjacent spiral metal lines. Furthermore, via plugs are formed in each dielectric layer to electrically connect two adjacent spiral metal lines. A spiral air trench is formed along the spacing of the spiral metal lines in the dielectric layers. Therefore, 3D-structure of the inductor of the invention can greatly reduce the series resistance thereof without widening the spiral metal lines. In addition, the spiral air trench, filled with air which has a lower dielectric constant, can efficiently reduce the parasitic capacitance between the spacing of the spiral metal lines. As a result, the inductor of the invention has a higher quality factor at a proper RF operating frequency region.

Abstract: A method for depositing copper on a titanium-containing surface of a substrate is provided. The method includes forming a patterned catalyst material on the substrate, such that the titanium-containing surface is exposed in selected regions. The catalyst material has an oxidation half-reaction potential having a magnitude that is greater than a magnitude of a reduction half-reaction potential of titanium dioxide. Copper is then deposited from an electroless solution onto the exposed regions of the titanium-containing surface.

Abstract: An integrated circuit die include a first portion including logic circuits. A second portion of the die includes an EEPROM memory, and a third portion includes a FLASH memory.

Abstract: A method for applying an underfill and edge coating to a flip chip is described. The method includes the steps of adhering a bumped wafer to an expandable carrier substrate, sawing the wafer to form individual chips, stretching the carrier substrate in a bidirectional manner to form channels between each of the individual chips, applying an underfill material to the bumped surfaces of the chips and around the edges of the chips, cutting the underfill material in the channels between the chips and removing the individual, underfill coated chips from the carrier.

Abstract: A method of forming an arsenic doped oxide layer in a process chamber is disclosed. The method comprises the steps of: setting the process chamber to a temperature of approximately 400-500° C. and a pressure of about 40-250 torr; flowing tetraethylorthosilicate (TEOS) into the process chamber; flowing triethylarsenate (TEAS or TEASAT) into the process chamber; and flowing ozone into the process chamber.

Abstract: A novel method of automatically routing connections from bumps on a die to package pins in an advanced IC package such as a flip-chip package. The method involves creating graphic presentations of the die having the bumps and the package having pins, and placing the graphic presentation of the die into the graphic presentation of the package. If a netlist identifying interconnections between the bumps and the pins is available, the best route from a bump on the die to a corresponding package pin identified in the netlist is generated in accordance with preset requirements. If the netlist is not available, the best route from the bump to any package pin is generated in accordance with the preset requirements.

Abstract: A process is provided for removing resist mask material from a protective barrier layer formed over a layer of low k silicon oxide dielectric material of an integrated circuit structure without damaging the low k dielectric material, and without the necessity of subjecting the exposed via sidewalls of the low k dielectric material to either a pretreatment to inhibit subsequent damage to the low k dielectric material during the resist removal, or a post treatment to repair damage to the low k material after the resist removal. The resist removal process comprises exposing the resist mask material to a hydrogen plasma formed from a source of hydrogen such as ammonia, while maintaining the temperature below about 40° C. to inhibit attack of the low k silicon oxide dielectric material by oxygen released from the decomposition of the resist material.

Abstract: A semiconductor die assembly comprising a semiconductor die with bond pads, a plurality of leads which extends across the semiconductor die and terminates over its respective bond pads, and an alpha barrier preferably positioned between the leads and the semiconductor die. Electrical connection is made between the leads and their respective bond pads by a strip of anisotropically conductive elastomeric material, preferably a multi-layer laminate consisting of alternating parallel sheets of a conductive foil and an insulating elastomer wherein the laminate layers are oriented perpendicular to both the bond pad and the lead, positioned between the leads and the bond pads. A burn-in die according to the present invention is also disclosed.

Abstract: A method of making a semiconductor chip assembly, including providing a dielectric element with a plurality of electrically conductive terminals, disposing an expander ring over the dielectric element so that a semiconductor chip on the dielectric layer is disposed in a central opening in the expander ring, and disposing an encapsulant in the gap between the expander ring and the semiconductor chip. The size of the gap is controlled to minimize the pressure exerted on the leads by the elastomer as it expands and contracts in response to changes in temperature. The semiconductor chip and expander ring may also be connected to a heat sink or thermal spreader with a compliant adhesive.

Abstract: A method to fabricate bottle-shaped deep trench into a semiconductor substrate. After a neck profile is formed, the chlorine gas at a predetermined flow rate is added to the etching plasma gas composition, while the flow rates of the plasma gases are increased by about 30% by volume, to create an enlarged lower portion of the deep trench. Preferably, the neck portion is etched using an etching composition which contains HBr, NF3, and (He/O2) provided at flow rates of about 87:13:35 sccm. The enlarged lower portion is etched using an etching composition which contains HBr, NF3, and (He/O2) provided at flow rates of about 113±12:17±2:46±5 sccm, and Cl2 provided at a flow rate between 10 and 40 sccm. It was found that the width of the lower portion of the deep trench can be increased by 100% with minimum side effects such as polymer deposition in the plasma chamber, which could occur as result of substantially increased flow rate of HBr and/or NF3.

Abstract: A condensed memory matrix is fabricated by conductively connecting the attachment bumps of a substrate with the attachment bumps of a wafer of DRAM chips and physically bonding the juxtaposed surfaces of the substrate and the wafer with a dielectric curable resin. An array of heat fins is bonded to the inactive surface of the wafer by a thermally conductive curable resin.

Abstract: A process of forming a bond pad structure, with a roughened top surface topography, used to improve the bondability of a gold wire bond, to the underlying bond pad structure, has been developed. The process features the use of a tungsten mesh pattern, formed in an IMD layer, and located underlying the bond pad structure, while overlying, and contacting, an underlying upper level, metal interconnect structure. The use of a tungsten mesh pattern, in place of individual tungsten studs, results in the creation of isolated islands, of IMED, reducing the bonding force, experienced by the IMD shapes, during the subsequent gold wire bond procedure. In addition the tungsten mesh pattern is formed via partial filling of a mesh pattern opening, in the IMD layer, resulting in an indented, or notched top surface. This in turn allows a roughened top surface, for the overlying bond pad structure, to be created, resulting in improved bondability of the gold wire, to the roughened top surface of the bond pad structure.

Abstract: An etching mask is made of a metal such as Permalloy (NiFe) and has a T-shaped cross section made up of a vertical bar having width W1 and a lateral bar having width W2. Through ion beam etching with the etching mask, the region in the surface of a workpiece not covered with the mask is selectively removed by the ion beams applied thereto. In the mask the vertical bar has a region obstructed by the lateral bar and a redeposit portion. As a result, the region of the vertical bar near the interface between the workpiece and the vertical bar that substantially determines the pattern width does not change in width. Consequently, a pattern of the workpiece on which etching has been performed has the top width and bottom width substantially equal to width W1 of the vertical bar of the mask. The pattern is rectangular in cross section.