Abstract: An integrated circuit chip carrier assembly, comprising a semiconductor device (10) having interconnection pads (14) disposed on an active surface (12) of the device. The device (10) is attached by means of electrically conducting bumps (26) to a circuitry pattern (18) on a first side of a circuit carrying substrate (16). The substrate is typically an aramid reinforced organic resin, such as epoxy. The circuitry (18, 20) is electrically connected by conductive through-holes (22) to an array of solder pads on a second side of the substrate. Some or all of the through-holes (22) are covered by the device. The overall length and width of the circuit carrying substrate (16) are each a maximum of about 0.15 inches greater than the equivalent dimensions of the device (10), creating a carrier that is only slightly larger than the semiconductor device itself.

Abstract: The structural body of a ferroelectric capacitor C is located over a source region (23) between a gate electrode (22) and a local oxide film (26). The structural body has a ferroelectric film (29) and an upper electrode (30) and a lower electrode (31) for sandwiching the ferroelectric film (29), and is provided with a conductive oxide film (32) between the lower electrode (31) and the source region (23). The conductive oxide film (32) is ITO, ReO.sub.2, RuO.sub.2 or MoO.sub.3. If an oxygen anneal is conducted after forming the ferroelectric film (29) for the purpose of reforming crystallizability of the ferroelectric film (29), oxygen enters into the conductive oxide film (32) to some extent. As a result, the conductive oxide film (32) is further oxidized, and becomes a so-called oxide barrier or dummy layer.

Abstract: Deformation of TAB tapes due to temperature changes is prevented by thermo-mechanical leads. In one embodiment of the invention, a semiconductor device (30) includes an electronic component (31) and a TAB tape. The tape includes a carrier film (12) and electrical leads (20) formed on the carrier film. The electrical leads are electrically coupled to the electronic component. Also included on the carrier film are thermo-mechanical leads (32) which are formed in opposing regions of the carrier film, regions which are typically void of leads. The thermo-mechanical leads have approximately the same lead pitch as the electrical leads in order to provide a uniform distribution of stresses across the TAB tape upon exposure to varying temperatures.

Abstract: A novel avalanche photodiode includes an n-type semiconductor substrate, an n-type light-absorbing layer on the substrate, an n-type multiplication layer on the light-absorbing layer, and a p-type light-receiving layer. The multiplication layer includes a plurality of pairs of semiconductor layers, with each pair including one high dopant impurity concentration layer and one low dopant impurity concentration layer.

Abstract: A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.

Abstract: A circuit element which includes a source region of a first conductance type provided with a source terminal, an intermediate region of the first conductance type separated from the source region by a first volume, a first channel region portion of a second conductance type provided with a first gate terminal and occupying the first volume, a drain region of the first conductance type provided with a drain terminal and separated from the intermediate region by a second volume, a second channel region portion of the second conductance type provided with a second gate terminal conductively connected to the first gate terminal and occupying said second volume, and an oxide layer. The first channel region portion, the intermediate region, and the second channel region portion are deposited on one face of the oxide layer. The design of the circuit element reduces adverse consequences of the so-called Kink effect, to which other circuit elements have been subject.

Abstract: A method for connecting devices on an integrated circuit substrate to a metallization layer, wherein a thin layer of a dielectric material is deposited on the substrate, and openings are formed in the dielectric layer wherein electrical connection is to be made to the substrate. A metal barrier layer then is deposited selectively in the openings of the dielectric layer, the barrier layer completely covering the exposed portions of the substrate. A pillar metal layer then may be deposited as a blanket coating over the dielectric layer and over the portions of he barrier layer covering the exposed portions of the substrate. The pillar metal layer is etched for forming metal pillars extending from the exposed portions of the substrate. The substrate then is planarized by depositing a dielectric layer and etching it back for exposing the pillars for coupling to a later deposited metallization layer.

Abstract: In a chip-carrier provided with a chip-carrier substrate, a chip-carrier cover and an IC chip, said IC chip being arranged at a distance from a circuit surface of the IC chip being directed toward the chip-carrier substrate, an .alpha.-ray shielding film made of film material containing few radioactive elements, and adhered to a surface of the chip-carrier substrate facing the IC chip or to the circuit surface of the IC chip is provided for protecting the IC chip from the IC chip.

Abstract: A semiconductor device including a substrate, a semiconductor element formed on the substrate, a terminal formed on the substrate and electrically connected to the semiconductor element, and a protective resistor formed on the substrate and electrically connected between the semiconductor element and the terminal. The resistor is composed of a ferromagnetic magnetoresistive material including Ni alloy. The device may be extended to detect magnetism by adding a magnetoresistive element composed of a ferromagnetic magnetoresistive material including the same Ni alloy as for the protective resistor and deposited at the same time. The device is superior in an anti-noise characteristic and is integrated. Furthermore, the device for detecting magnetism is formed with a lower cost.

Abstract: A semiconductor mounting package is provided which permits the active p-n junction of a light emitting semiconductor to be operated in a liquid heat transfer fluid. The package provides optical coupling for extracting light energy.

Abstract: Epoxy bonding between an IC chip and a chip carrier is strengthened by creating substantially rougher oxidized surfaces within substantially smooth gold surfaces of a die paddle portion of the chip carrier.

Abstract: A method for manufacturing an EEPROM comprises the step of using raw gas containing an organic compound having a molecular weight of more than 44, such as ethyl acetate and tetrahydrofuran when a first polysilicon layer serving as a select gate electrode and a second polysilicon layer serving as a floating gate electrode are deposited by a CVD process. The above described step allows a voltage at the time of tunneling electrons to be decreased.

Abstract: A multichip integrated circuit package comprises a substrate having a flat upper surface to which is affixed one or more integrated circuit chips having interconnection pads. A polymer encapsulant completely surrounds the integrated circuit chips. The encapsulant is provided with a plurality of via openings therein to accommodate a layer of interconnection metallization. The metallization serves to connect various chips and chip pads with the interconnection pads disposed on the chips. In specific embodiments, the module is constructed to be repairable, have high I/O capability with optimal heat removal, have optimized speed, be capable of incorporating an assortment of components of various thicknesses and function, and be hermetically sealed with a high I/O count. Specific processing methods for each of the various module features are described herein, along with additional structural enhancements.

Abstract: A depletion operation is realized by using a depletion type MOSFET even at the room temperature or the liquid nitrogen temperature without doping the channel portion below the gate electrode with impurities having a conductivity type, which is opposite to the conductivity type of the semiconductor substrate. Further this FET can construct an inverter together with an enhancement type FET and these can be integrated on one substrate.

Abstract: A phototransistor includes a monocrystalline semiconductor substrate of a first conductivity type, a crystalline semiconductor layer of a second conductivity type formed from a surface of the semiconductor substrate to a predetermined depth, a substantially intrinsic amorphous semiconductor layer formed on the crystalline semiconductor layer, and an amorphous semiconductor layer of the first conductivity type formed on the intrinsic amorphous semiconductor layer.

Abstract: A transistor having a high carrier mobility and suited for a high-speed operation can be formed by utilizing a fact that the carrier mobility in a strained germanium layer is large. A strain control layer is provided beneath the germanium layer to impose a compressive strain on the germanium layer, and the composition of the strain control layer in a predetermined range is used to generate the compressive strain surely.

Abstract: A semiconductor device includes a specific circuit portion having a predetermined function and a spare redundant circuit portion having the same function as the specific circuit portion. The semiconductor device includes a silicon substrate (1), an interlayer insulating film (2), an LT fuse (3), interconnection layers (4), a testing electrode (5) and a protection film (6). The interlayer insulating film (2) has a groove (11) and is formed on the silicon substrate (1). The LT fuse (3) is formed of polysilicon and is located immediately below the bottom wall of the groove (11). The interconnection layers (4) are formed on the interlayer insulating film (2) with the groove (11) therebetween. The testing electrode (5) is spaced from the interconnection layers (4) and is formed on the interlayer insulating film (2). The protection film (6) is formed on the interlayer insulating film to cover surfaces of the interconnection layers (4) and expose a surface of the testing electrode (5).

Abstract: A method of forming self-aligned transistors which may be either bipolar or field effect is described. A heavily doped conductive layer of one conductivity type is formed upon a monocrystalline semiconductor substrate of the opposite conductivity type to that of the one type. The conductive layer may be polycrystalline silicon, tungsten silicide, titanium nitride or the like. An insulator layer is formed upon the surface of the conductive layer. Openings with substantially vertical sidewalls are formed through the conductive layer to the semiconductor substrate in at least the locations of the first element of the transistors to be formed. The structure is heated to form the heavily doped portions of the second element of said transistors of the one conductivity type by outdiffusing from the conductive layer.

Abstract: The invention relates to a photocoupler comprising a light emitting element and a light receiving element, the light emitting element having a first and a second electrode in electrical contact with a first and a second contact pin, respectively, by means of which the light emitting element is fixed in position, the light receiving element having a third and a fourth electrode in electrical contact with a third and a fourth contact pin, respectively, by means of which the light receiving element is fixed in position. The light emitting element and the light receiving element are situated opposite one another and enveloped in a first solid and transparent layer, surrounded at least in part by a second solid layer provided in such a manner as to reflect the light.

Abstract: In a DRAM having stacked capacitor cells, elements are isolated by field shield isolating structure. The field shield isolating structure is formed surrounding both X and Y directions of the memory cell in the DRAM. The field shield isolating structure comprises an isolating electrode layer formed on a semiconductor substrate between adjacent memory cells with an insulating film interposed therebetween. Two impurity regions included in the adjacent memory cells and the isolating electrode layer constitute a MOS transistor. A voltage for maintaining the MOS transistor normally-off is applied to the isolating electrode layer. A portion of the stacked capacitor extends to the isolating electrode layer. One of the source/drain regions of the MOS transistor is formed in self-alignment, using a sidewall spacer formed of an insulating film on a sidewall of the field shield electrode as a mask.