Abstract: An interference cancellation repeater for canceling an interference signal included in an input signal including a first adaptive filter configured to generate a first estimated signal; a second adaptive filter configured to generate a second estimated signal; a first scaler configured to scale the first estimated signal based on a first scale factor determined according to a channel state; a second scaler configured to scale the second estimated signal based on a second scale factor determined according to the channel state; a first canceller configured to generate a first interference canceled signal based on the input signal and the scaled first estimated signal; and a second canceller configured to generate a second interference canceled signal based on the first interference canceled signal and the scaled second estimated signal.

Abstract: An apparatus for a multiple-input multiple-output (MIMO) architecture is disclosed. The apparatus includes a first splitter-combiner (S-C) having a first transmission line port, a first transmit (TX) port, and a first receive (RX) port. Also included is a first N-plexer having a first power amplifier (PA) input, a first RX output, and a first antenna output for coupling to a first antenna. A first PA is coupled between the first TX port and the PA input, wherein the first RX output is coupled to the first RX port.

Abstract: A burst mode clock data recovery device includes a clock data recovery loop, a frequency tracking loop, a frequency tracking loop, and a fast-locking unit. The clock data recovery loop receives a sampling clock signal and a data signal and uses the sampling clock signal to lock the data signal to generate a recovery clock signal. The frequency tracking loop tracks a frequency of the recovery clock signal to generate a frequency detection signal associated with the recovery clock signal. The phase lock loop receives the frequency detection signal and locks the recovery clock signal in a reference clock. The fast-locking unit generates a fast-locking signal according to the recovery clock signal and a first phase detection signal to allow the clock data recovery loop to quickly lock the data signal after the transition from a stall mode to the burst mode.

Abstract: The method includes converting, by the receiver, an input signal into a return-to-zero (RZ) signal, generating, by the receiver, a first summation signal by performing an exclusive-or (XOR) operation on the RZ signal and a delayed signal obtained by delaying the RZ signal by a reference time, collecting, by the receiver, n-length seed codes from the first summation signal, generating, by the receiver, a PN code based on the seed codes, and generating, by the receiver, a second summation signal by performing an XOR operation on the PN code and the delayed signal.

Abstract: A compensation circuit in a MIMO system includes a phase shifting circuit and an attenuation circuit. The phase shifting circuit includes a plurality of phase shifters coupled in parallel which apply compensation to signals. The attenuation circuit includes a plurality of attenuators coupled in parallel to apply compensation to signals.

Abstract: A clock and data recovery device includes a data sampling module, a phase detection circuit, a frequency estimator, a clock generation module, and a data recovery module. The data sampling module samples input data according to first clock signals to generate data values, in which phases of the first clock signals are different from one another. The phase detection circuit detects a phase error of the input data according to at least one second clock signal, to generate an error signal. The frequency estimator generates an adjustment signal according to the error signal, a phase threshold value, and a frequency threshold value. The clock generation module generates the first clock signals and the at least one second clock signal according to the adjustment signal and a reference clock signal. The data recovery module generates recovered data corresponding to the input data according to the data values.

Abstract: Certain implementations of the disclosed technology may include systems and methods for data alignment without requiring an external synchronizing trigger. A method is provided that can include receiving a signal that represents a plurality of frames, each of the plurality of the frames include an optional data portion and a predetermined portion. The method includes sampling and buffering at least a portion of the received signal to produce a buffered digital sequence. The method includes processing, by a sequence alignment module, the buffered digital sequence using a known sequence, where the known sequence corresponds to the predetermined portion. The method includes determining, using the sequence alignment module, respective positions of the buffered digital sequence corresponding to the known sequence, comparing the known sequence with the buffered digital sequence at the respective determined positions, and outputting one or more parameters based at least in part on the comparing.

Abstract: Compression control of cascode power amplifiers. A power amplifier module can include a power amplifier including a cascode transistor pair. The cascode transistor pair can include a first transistor and a second transistor. The power amplifier module can include a current comparator configured to compare a first base current of the first transistor and a second base current of the second transistor to generate a comparison signal. The power amplifier module can include a saturation controller configured to maintain the power amplifier out of saturation based on the comparison signal.

Abstract: Quasi-reduced state trellis equalization techniques achieve low-latency inter-symbol interference (ISI) equalization by selecting a subset of accumulated path metrics (APMs) for a leading symbol to propagate over a trellis to candidate states of a trailing symbol. This simplifies the computation of APMs for candidate states of the trailing symbol. Thereafter, APMs for candidate states of the trailing symbol are computed based on the subset of APMs for the leading symbol that were propagated over the trellis. Propagating fewer than all APMs for the leading symbol to the trailing symbol reduces the complexity of APM computation at the trailing symbol.

Abstract: In a multi-user communication system, a pre-coder in a transmitter comprises a Discrete Fourier Transform (DFT) spreader configured to spread data symbols with Fourier coefficients to generate DFT-spread data symbols. An OFDM modulator, such as an inverse-DFT, modulates the DFT-spread data symbols onto OFDM subcarriers to produce a pre-coded OFDM transmission signal. The DFT spreader is configured to reduce the transmission signal's peak to average power.

Abstract: Some embodiments relate to a method and circuit for gain compensation. The method includes detecting a strength of an output signal generated by a power amplifier of a transmitter in response to a commanded transmission signal. The method also includes comparing the detected strength of the output signal to a delayed version of a detected strength of the commanded transmission signal to obtain an error signal. The method further includes compensating for gain drop of the output signal by adjusting a gain of the transmitter based on the error signal.

Abstract: One example includes a rate detector system. The rate detector system includes a plurality of energy detectors configured to receive an input signal and to filter separate respective frequency bands associated with the input signal to generate separate respective energy profiles. The system also includes an energy processing component configured to determine a symbol rate of the input signal based on a statistical evaluation of a ratio of the separate respective energy profiles.

Abstract: Methods and apparatuses for Orthogonal Frequency-Division Multiplexing (OFDM) communication of non-OFDM radio signals are disclosed. The non-OFDM radio signals are force-modulated into OFDM signals. In one example, a non-OFDM signal is received and is processed into an OFDM signal to produce a created OFDM signal. An actual OFDM signal is also received and is processed together with the created OFDM signal.

Abstract: In a transmission device, a coder performs SFBC block coding of a signal stream includes a divider equally dividing the stream into sub-streams of time lengths Msub and performs a cyclic shift of one or more sub-streams, a processor outputs the sub-streams and performs, on the sub-streams, time-axis inversion processing, complex conjugate processing and sign inversion processing, or the time-axis inversion processing and the complex conjugate processing, a phase rotation unit generates a repetitive signal of a time length N in which an output signal of the processor is reproduced and arranged, and giving phase rotation to the repetitive signal, and a multiplexer generates, for each transmission antenna, a signal transmitted from the antenna, by multiplexing the repetitive signals given the phase rotation, and the unit gives different phase rotations to repetitive signals multiplexed to an identical transmission signal.

Abstract: The estimation and mitigation of swept-tone interferers includes receiving a composite signal comprising a signal of interest and a swept-tone interferer over an observation bandwidth or a hop bandwidth in a frequency-hopping system. The estimation of the interfering signal may be based on modeling the interferer as a magnitude periodic signal comprising non-overlapping, contiguous epochs, where each epoch may comprise a common pulse shape and a distinct phase rotation. The modeling may be based over the observation bandwidth, the hop bandwidth, or after combining the signal over all the frequency hop bandwidths. The period of the magnitude-periodic signal may be initially determined, and the common pulse shape and each of the distinct phase rotations may then be estimated. These estimates may be used to reconstruct an estimate of the swept-tone interferer, which may be subtracted from the composite signal to generate an interference-mitigated signal of interest.

Abstract: An apparatus for processing data includes a linear equalizer, a load switchably connected to an output of the linear equalizer, a slicer configured to sample a signal derived from the output of the linear equalizer, and a detector circuit configured to detect an over-equalization condition in data to be sampled by the slicer and to connect the load to the output of the linear equalizer in the over-equalization condition.

Abstract: An electronic device includes a signal sender that sends a pair of transmission signals of mutually opposite phases to an external device via a pair of transmission paths. The signal sender differentiates each amplitude of the pair of transmission signals.

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

Abstract: A method, system and apparatus for modelling a power amplifier and pre-distorter fed by one of a wideband signal and an intra-band carrier aggregated signal are disclosed. According to one aspect, a method includes receiving the one of the wideband signal and the intra-band carrier aggregated signal and generating a discrete base band equivalent, BBE, Volterra series based on the received signal, where the series has distortion products grouped according to determined shared kernels. The shared kernels are determined based on a transformation of a real-valued continuous-time pass band Volterra series without pruning of kernels.

Abstract: The present document is for a wireless communication with reduced internal signaling burden in the distributed antenna system (DAS). In the proposed method, a user equipment (UE) receives signals, from the network, by multiple distributed unit (DUs) distributed within the UE, wherein the multiple DUs comprise one or more main DUs and one or more sub DUs; reports, by the sub DUs, first reception information of the signals to one of the main DUs; reports, by the one of the main DUs, second reception information of the signals to a central unit (CU) controlling the multiple DUs based on the first reception information of the signals; and determines, at the CU, which one or more DUs among the multiple DUs are to transfer the received signals to the CU based on the second reception information of the signals.