Abstract: Method of forming a termination angle in a titanium tungsten layer include providing a titanium tungsten layer and applying a photo resist material to the titanium tungsten layer. The photo resist material is exposed under a defocus condition to generate a resist mask, wherein an edge of the exposed photo resist material corresponds to the sloped termination. The titanium tungsten layer is etched with an etching material, wherein the etching material at least partially etches the photo resist material exposed under the defocused condition, and wherein the etching results in the sloped termination in the titanium tungsten layer.

Abstract: A semiconductor memory device according to an embodiment comprises: a plurality of memory strings arranged in a first direction intersecting a surface of a semiconductor substrate, each of the memory strings including a plurality of memory transistors connected in series in a second direction along the surface of the semiconductor substrate; a source side select transistor connected to one end of the memory string; a drain side select transistor connected to the other end of the memory string; a plurality of source lines respectively connected, via the source side select transistor, to each of the plurality of memory strings arranged along the first direction; a bit line commonly connected, via the drain side select transistor, to the plurality of memory strings arranged along the first direction; a word line connected to a gate electrode of the memory transistor; and a layer selector disposed between the source line and the source side select transistor and commonly connected to the plurality of memory strin

Abstract: An organic light emitting display device and a method of manufacturing the same are proposed. The organic light emitting display device includes: a first film formed of an organic material, and having first and second surfaces facing each other and a third surface perpendicular to the first and second surfaces; a second film formed on the first film to cover the second and third surfaces of the first film; an organic light emitting unit disposed on the second film; a third film disposed on the second film to cover the organic light emitting unit; and a fourth film disposed on the third film, formed of an organic material, and having fourth and fifth surfaces facing each other, wherein the fifth surface faces the third film.

Abstract: A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET entails laterally recessing the strained fin in the source and drain regions using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the widths of fin portions in the source and drain regions to less than 5 nm. The resulting FinFET features a wide portion of the fin in the channel region underneath the gate, and a narrower portion of the fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions.

Abstract: The present disclosure relates to an integrated circuit (IC). The IC includes a substrate, which includes a periphery region having a first substrate surface and a memory cell region having a second substrate surface. The second substrate surface is recessed within the substrate relative to the first substrate surface. A high k metal gate (HKMG) transistor is disposed on the first substrate surface and includes a HKMG gate. Two neighboring flash memory cells are disposed on the second substrate surface and include a pair of flash memory cell control gates. Top surfaces of the HKMG gate and flash memory cell control gates are co-planar.

Abstract: A light-emitting device and a lighting device each of which includes a plurality of light-emitting elements exhibiting light with different wavelengths are provided. The light-emitting device and the lighting device each have an element structure in which each of the light-emitting elements emits only light with a desired wavelength, and thus the light-emitting elements have favorable color purity. In the light-emitting element emitting light (?R) with the longest wavelength of the light with different wavelengths, the optical path length from a reflective electrode to a light-emitting layer (a light-emitting region) included in an EL layer is set to ?R/4 and the optical path length from the reflective electrode to a semi-transmissive and semi-reflective electrode is set to ?R/2.

Abstract: Methods of forming high voltage (111) silicon nano-structures are described. Those methods and structures may include forming a III-V device layer on (111) surface of a silicon fin structure, forming a 2DEG inducing polarization layer on the III-V device layer, forming a source/drain material on a portion of the III-V device layer on terminal ends of the silicon fin. A middle portion of the silicon fin structure between the source and drain regions may be removed, and backfilled with a dielectric material, and then a gate dielectric and a gate material may be formed on the III-V device layer.

Abstract: A semiconductor device includes a semiconductor substrate divided into a first area and a second area, the semiconductor substrate including a first dopant of a first type, a first well formed to a first depth in the first area of the semiconductor substrate, the first well including a second dopant of a second type, wherein the second type is different from the first type, a second well including a third dopant of the first type, the second well being surrounded by the first well, and a pipe gate formed on the first area of the semiconductor substrate, the pipe gate being electrically connected to the second well.

Abstract: A member peeling method includes a step for preparing a first member having a first main face and an outer edge thereof and a second member having a second main face and an outer edge thereon, a step for disposing a photothermal conversion layer on at least one portion of the outer edge on the first main face, a step for mutually joining the first main face and the second main face via an adhesive layer, a step for irradiating a laser light to the photothermal conversion layer, and a step for at least partially peeling the first member from the second member by applying a force to an outer peripheral portion of either of the first member or the second member in a direction away from the other member.

Abstract: The present invention provides a pixel array, a display panel and a display device, and the pixel array includes a plurality of gate lines and a plurality of data lines intersecting and insulated from each other, and a plurality of pixel units defined by the plurality of gate lines and the plurality of data lines intersecting each other. Each of the plurality of pixel units includes a thin-film transistor and a strip-shaped electrode, the strip-shaped electrodes of two adjacent pixel units in a same column have different inclination directions, the thin-film transistors of the two adjacent pixel units are in inclination angle regions of the two adjacent pixel units, respectively, and the inclination angle region is a region corresponding to a position at which extending directions of the strip-shaped electrode and the gate line intersect to form an acute angle in a pixel unit.

Abstract: A trench having an opening and a corner portion is formed in a silicon carbide substrate. A corner insulating film is formed to cover the corner portion. A gate insulating film is formed to cover a region extending from the opening to the corner portion. The step of forming the gate insulating film includes a step of thermally oxidizing the trench provided with the corner insulating film. The step of thermally oxidizing the trench includes a step of heating the silicon carbide substrate at not less than 1300° C. Accordingly, sufficient insulation reliability of the gate insulating film is secured near the opening of the trench while preventing dielectric breakdown of the gate oxide film at the bottom portion of the trench.

Abstract: The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.

Abstract: A transistor device includes an array of fin structures arranged on a substrate, each of the fin structures being vertically alternating stacks of a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point; one or more carbon nanotubes (CNTs) suspended between the fin structures and contacting a side surface of the second isoelectric point material in the fin structures; a gate wrapped around the array of CNTs; and source and drain contacts arranged over the fin structures; wherein each of the fin structures have a trapezoid shape or parallel sides that are oriented about 90° with respect to the substrate.

Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.

Abstract: A resistive random access memory (RRAM) cell comprises a transistor having a gate and a source/drain region, a bottom electrode coplanar with the gate, a resistive material layer over the bottom electrode, a top electrode over the resistive material layer, and a conductive material electrically connecting the bottom electrode to the source/drain region.

Abstract: The present application discloses a package cover plate for packaging a curved display panel comprising at least two curved portions.

Abstract: This disclosure is directed to techniques for fabricating CMOS devices for SRAM cells with resistors formed along transistor well sidewall edges by self-aligned, angled implantation, which may enable more compact SRAM architecture with SEU mitigation, such as for space-based or other radiation-hardened applications. An example method includes implanting a dopant into a doped semiconductor well covered by a barrier, wherein the doped semiconductor well is disposed on a buried insulator and wherein the dopant is of opposite doping type to the doped semiconductor well, thereby forming a resistor on an edge of the doped semiconductor well, wherein the resistor has the opposite doping type. The method further includes forming a second insulator adjacent to the resistor, removing the barrier, and forming agate layer on the doped semiconductor well, thereby forming a gate adjacent to the doped semiconductor well and the resistor.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor layer, a first electrode, first and second oxide layers, and a storage layer. The first oxide layer is provided between the semiconductor layer and the first electrode. The second oxide layer is provided between the first oxide layer and the first electrode. The storage layer is provided between the first and second oxide layers. The storage layer includes a first region including silicon nitride, a second region provided between the first region and the second oxide layer and including silicon nitride, and a third region provided between the first and second regions. The third region includes a plurality of first metal atoms. A first density of bond of the first metal atoms in the third region is lower than a second density of bond of the first metal atom and a nitrogen atom in the third region.

Abstract: The present invention provides a manufacture method of a black matrix. The COA technology is utilized to manufacture the organic photoresist blocks with a larger thickness on the alignment marks. Then, the black matrix thin film covers on the organic photoresist blocks to tremendously increase the level differences of the positions of the alignment marks and adjacent areas. Thus, the contour recognition apparatus is employed to accurately recognize positions of the alignment marks. The issue that the alignment marks are difficult to be recognized after the black matrix thin film is coated in the BOA process can be solved.

Abstract: Stacked planar capacitor structures and methods of fabricating the same generally include stacking two or more capacitors with three electrodes by sharing a middle electrode, wherein each capacitor has a different area. The stacked structure does not include step heights, which permits fabrication of multiple structures where desired.