Abstract: A programmable logic device has a high level counter element and a programmable AND array suitable for control applications. Moore and Mealy state machines are readily implemented by the controller by virtue of its programmable AND array and counter which allow the next-state and output to be based on the contents of the counter as well as any set of input signals. Conditional testing can be made entirely state dependent, partially-state dependent, or state-independent. Multiway branching is also readily implemented since the presence of the programmable AND array allows the user to specify a number of sets of input conditions, so that from a given state, as determined by the counter contents, each set of input condition gives rise to a transition to a specified next state. Instructions can be stored in the AND array in a logical form directly useable by the hardware.

Abstract: A method for partitioning an original string of data elements into two substrings on a distributed processing system is disclosed. The elements are each of a first or a second type and the original string consists of a plurality of string fragments each composed of elements of only one type. The method operates to pass the identity of each fragment tail element to the head element of the next fragment, further from a true head element of the original string, composed of the same type elements as the tail element. The passed identities enable forming the two substrings from fragments of the same type elements.

Abstract: System for analyzing programs by measuring the degree of code coverage of a program being tested during specific test phases. A correlation and comparison of results obtained from both a static and dynamic analysis recording is made. The introduction of a static and dynamic instruction flow indicator permits a determination of the test cover results by correlating the data of the static and dynamic instruction flow indicators. Thus, the number of untested functions can be determined during a test phase of a computer program before sending the data processing system to the field.

Abstract: In the present invention, data input/output equipment is connected in communication with a host machine which provides a plurality of service application programs by designating system parameters of one or more common programs. A mode setting feature designates at least a program setting mode and an execution mode. A program RAM stores at least one common program being loaded from the host machine. A parameter setting feature designates parameters included in the common program loaded in the program setting mode to define a plurality of application programs, each of which is available for a specified service. A parameter RAM memorizes the designated parameters. An entry data RAM memorizes entry data, and a service selecting feature designates one of the application programs in the execution mode.

Abstract: A data processing apparatus for image display includes a character generator, a bit map type image memory, a CPU for accessing the character generator and the image memory to control the data stored in the image memory, a display, and a display controller for reading out the data stored in the image memory in accordance with a command from the CPU and supplying the readout data to the display. The image display apparatus further includes an image memory controller having a barrel shifter for parallelly shifting the data supplied from the CPU by a designated number of bits, a mask controller for outputting a mask data to restrict a write range of the data supplied from the CPU and a write controller for operatively combining the data from the barrel shifter and the data read from the image memory in accordance with the mask data to prepare a write data and supplying the write data to the image memory.

Abstract: A channel analyzer system has circuits for passive coupling to individual signal lines on a computer data channel, and for monitoring the data passed thereover, with logic circuits having preselectable capability for recognizing transmitted data of interest for further analysis. The system further includes a large storage capability for retaining preselected amounts of data, examining blocks of data so collected and recorded, labeling data samples with an identifier; displaying selected portions of the samples, including representative values signifying the data content and preselected signal line changes of interest, data channel activity prior to and subsequent to the preselected signal line event which is of interest; and displaying the same for providing a visualized summary of activity of a computer channel according to the protocols defined for the channel activity.

Abstract: An information processing apparatus having an address translation system includes a plurality of processors in each of which an addressing is carried out by translating a logical address into a real address in the virtual storage system for data processing. The plurality of processors include a scalar processor for translating a logical address into a real address by using an address translation table; and a vector processor for determining if the logical address to be relocated lies within a predetermined address range, for address-relocating the logical address to the real address based on a relocation table when the logical address lies within the predetermined address range, and using the logical address as a real address when the logical address lies outside of the predetermined address range. The predetermined address range and the content of the relocation table are set by the scalar processor which supervises the program storage area.