Abstract: A semiconductor integrated circuit comprises a first MOS transistor of a first conductivity type having one of its source and drain connected to a first signal input node, having the other thereof connected to a signal output node, and receiving a select signal at its gate; a second MOS transistor of a second conductivity type in parallel connection with the first MOS transistor, and receiving an inverted signal of the select signal; and a third MOS transistor of the second conductivity type having one of its source and drain connected to a second signal input node, having the other thereof connected to the signal output node, and receiving the select signal at its gate, the semiconductor integrated circuit being configured to satisfy the relation as expressed by an inequality W1>W2 where W1 and W2 are gate widths of the first and second MOS transistors.