Patents Examined by Daniel D Tsui
  • Patent number: 11861180
    Abstract: A memory system includes a plurality of non-volatile memory chips and a controller configured to communicate with a host and control the plurality of non-volatile memory chips. The controller is configured to write a data frame that includes write data and a first parity for error detection and correction of the write data into first memory chips of the non-volatile memory chips in a distributed manner. The first memory chips includes N (N is a natural number of two or more) memory chips. The controller is configured to write a second parity for restoring data stored in one of the N first memory chips using data read from the other N?1 of the N first memory chips, into a second memory chip of the non-volatile memory chips that is different from any of the first memory chips.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: January 2, 2024
    Assignee: Kioxia Corporation
    Inventor: Akiyuki Kaneko
  • Patent number: 11853099
    Abstract: While a connection between a copy pair comprising a primary volume in a first storage system associated with a primary host and a secondary volume in a second storage system associated with a secondary host is disconnected, systems and methods described herein can involve changing a state of the copy pair for each of the primary volume and the secondary volume to a temporary suspended state; detecting whether a network connection has recovered; for the detecting indicative of the network connection having recovered, changing the state of the copy pair for the each of the primary volume and the secondary volume to a copy pair state; and for the detecting indicative of the network connection not being recovered after a threshold period of time has elapsed, changing the state of the copy pair for the each of the primary volume and the secondary volume to a suspended state.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: December 26, 2023
    Assignee: HITACHI, LTD
    Inventor: Tomohiro Kawaguchi
  • Patent number: 11853588
    Abstract: A method includes: receiving, at a cluster controller of a first cluster, a request for pairing a first datastore of the first cluster to a second datastore of a second cluster, wherein each of the first cluster and the second cluster includes a plurality of datastores; determining whether the first datastore is available for pairing; in response to determining that the first datastore is available for pairing, generating an entry in a mapping table indicating that the first datastore is paired with the second datastore; receiving information associated with the second datastore; and in response to receiving the information, storing the information in the first datastore. The second cluster performs similar operations as those performed by the first cluster to achieve a bidirectional reservation between the first cluster and the second cluster.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: December 26, 2023
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Geetha Srikantan, Vishwas Srinivasan, Suman Saha
  • Patent number: 11847354
    Abstract: A sliding window cache can be used for data storage in a data grid. For example, a computing device can receive a request from a client device for storing a data entry in a data grid. The computing device can store the data entry in a first data set including a plurality of data entries distributed across a plurality of nodes of the data grid. The computing device can also store the data entry in a second data set in a sliding window cache that is embedded in the data grid. The second data set can include a subset of the plurality of data entries synchronized with the plurality of data entries of the first data set. The computing device can determine a statistic measurement associated with the sliding window cache and output the statistic measurement to the client device.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: December 19, 2023
    Assignee: RED HAT, INC.
    Inventors: Vittorio Rigamonti, Tristan Tarrant
  • Patent number: 11847344
    Abstract: A base die is configured to receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on the first data to generate a second encoded data, and transmit a second data to a memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data. The base die is further configured to receive the second data from the memory die in a reading phase, perform a first error checking and correction processing on the first data and the second encoded data, and transmit a third data in the reading phase.
    Type: Grant
    Filed: May 1, 2022
    Date of Patent: December 19, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shu-Liang Ning
  • Patent number: 11847021
    Abstract: An operation method of memory device, comprising: selecting a target block for performing an error correction operation; reading the target block row by row; transmitting the read data to an error correction circuit; and checking and correcting read data to generate a corrected data.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: December 19, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee
  • Patent number: 11842063
    Abstract: Software defined storage service (SDS) provides users with remote data volumes spread across multiple storage nodes across multiple failure domains. A distributed volume may be spread across replicas (e.g., failure domains), each replica having a number of partitions stored on storage nodes associated with a particular failure domain. In the event of a node failure, a partition stored on the failed node may be dynamically moved and remapped to another node in the same failure domain or within another failure domain that is different from a failure domain that includes a partition that is complementary to the partition stored on the failed node. The partition move and remapping may be transparent to a user. A partition move may occur while a distributed volume is in use by a client device or in an idle (e.g., offline) mode.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: December 12, 2023
    Assignee: EBAY INC.
    Inventors: Sami Ben Romdhane, Sakib Md Bin Malek, Tariq Mustafa, Jiankun Yu
  • Patent number: 11842067
    Abstract: A memory controller includes a read operation controller, an error correction circuit, and a read voltage controller. The read operation controller controls a memory device to read pieces of data from a selected page of the memory device by read voltages having different levels. The error correction circuit determines fail bit numbers of the pieces of data. The read voltage controller selects a reference voltage variation from among voltage variations included in a first read voltage table, based on an erase write cycle count of the memory device, and a reference fail bit number indicating a largest fail bit number of the fail bit numbers, and adjusts a level of each of the read voltages based on the reference voltage variation and a ratio value of a corresponding one of the fail bit numbers to the reference fail bit number.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: December 12, 2023
    Assignee: SK hynix Inc.
    Inventor: Jong Soon Leem
  • Patent number: 11829608
    Abstract: A resynchronization operation (300) adapts according to activity histories (148) within a storage platform (100). An owner node (A) and a backup storage node (B) may track activity such as the IO operations begun and use recent activity to determine respective amounts of data the owner (A) and backup (B) can expect to process without unacceptably degrading storage services. The owner (A) transfer resynchronization data in chunks, each having a size limited by the current amounts the owner (A) and backup (B) determined from current activity. When activity is low or idle, large chunks may be sent to quickly complete resynchronization, while a busy system uses smaller chunks such that the system performance is not adversely affected.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: November 28, 2023
    Assignee: Nebulon, Inc.
    Inventors: Siamak Nazari, Anil Swaroop, Srinivasa Murthy
  • Patent number: 11829644
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: receiving a read command from a host system; in response to a first physical erasing unit being a first type physical unit, sending a first operation command sequence to instruct a rewritable non-volatile memory module to read a first physical programming unit based on a first electronic configuration; and in response to the first physical erasing unit being a second type physical unit, sending a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration. The first electronic configuration is different from the second electronic configuration.
    Type: Grant
    Filed: January 22, 2022
    Date of Patent: November 28, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Po-Cheng Su, Chih-Wei Wang, Yu-Cheng Hsu, Wei Lin
  • Patent number: 11822807
    Abstract: A method of replication in a distributed storage system, performed by the distributed storage system is provided. The method includes managing a first index for data or metadata in a first storage system, the first storage system having a first partitioning scheme. The method includes managing a second index for data or metadata in a second storage system, the second storage system having a second partitioning scheme. The method includes replicating the data or metadata from the first storage system to the second storage system, translating an identifier of the data or metadata from the first storage system, and mapping the replicated data or metadata into the second partitioning scheme, via the translating of the identifier of the data or metadata from the first storage system.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: November 21, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Richard A. Hankins, Igor Ostrovsky, John Colgrove, Cary A. Sandvig, Ronald Karr, Victor Yip, Zong Miao, Abhishek Jain
  • Patent number: 11816340
    Abstract: Techniques are provided for increasing resiliency of IO operations to network interruptions. One method comprises, in response to a failure of a given IO operation on a first path between at least one initiator of a host device and at least one storage target of a storage volume of a distributed storage system, resending the given IO operation on a second path between the at least one initiator and the at least one storage target; and, in response to a completion of the given IO operation on a given one of the first path and the second path, initiating a remapping of the storage volume. The remapping of the storage volume may comprise unmapping the storage volume and mapping the storage volume. One or more IO operations having an older generation number than the generation number of the storage volume may be discarded.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: November 14, 2023
    Assignee: Dell Products L.P.
    Inventors: Tal Abir, Oshri Adler
  • Patent number: 11809272
    Abstract: A computer-implemented method and a serially-attached memory device for performing the method are provided. The method includes a memory device controller receiving data over an error-protected serial link from a host processor, wherein the memory device controller is included in a serially-attached memory device along with memory media coupled to the memory device controller. The method further includes the memory device controller storing the received data in the memory media coupled to the memory device controller, the memory device controller calculating error correction code for the received data, and the memory device controller storing the error correction code in the memory media coupled to the memory device controller.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: November 7, 2023
    Inventor: Jonathan Hinkle
  • Patent number: 11789864
    Abstract: A method of operating a Solid-State Drive (SSD) includes determining optimized thresholds of each corresponding segments according to their frequency of use, and executing a flush operation to write the one of the corresponding segments into a memory device according to the optimized thresholds of the corresponding segments.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: October 17, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Lei Zhang, Keke Ding, Li Wei Wang
  • Patent number: 11789766
    Abstract: Disclosed herein are systems and method for selectively restoring a computer system to an operational state. In an exemplary aspect, the method may include creating a backup image of the computer system comprising a set of data blocks, detecting that the computer system has begun an initial startup, identifying a subset of the data blocks read from a disk of the computer system during the initial startup. In response to determining that the computer system should be restored, the method may include restoring the subset of the data blocks such that the computer system is operational during startup, and restoring a remaining set of the data blocks from the backup image after the startup of the computer system.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: October 17, 2023
    Assignee: Acronis International GmbH
    Inventors: Alexey Sergeev, Anton Enakiev, Vladimir Strogov, Serguei Beloussov, Stanislav Protasov
  • Patent number: 11782648
    Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: October 10, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Amir Shaharabany, Eliad Adi Klein
  • Patent number: 11782630
    Abstract: A method and a computer system for asymmetric replication of data are provided. Storage of a set of data is organized as a first copy and as a second copy in non-volatile storage. The second copy is reliable and stored so as to be readable at a speed slower than for the first copy. A read instruction regarding the set of data is received and performed preferentially via the first copy such that the asymmetric replication achieves enhanced performance speed. A request to execute a write operation is received. The write operation is executed to the first copy and to the second copy. In response to determining that the write operation to the first copy was unsuccessful, a label for the first copy is set as stale.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: October 10, 2023
    Assignee: International Business Machines Corporation
    Inventors: Frank Schmuck, Owen T. Anderson, Deepavali M. Bhagwat, Enci Zhong, Felipe Knop, John Lewars, Hai Zhong Zhou, D Scott Guthridge
  • Patent number: 11775194
    Abstract: A data storage method implemented by a storage node in a distributed storage system includes receiving first data of a first strip in a first stripe, wherein the first stripe comprises a first plurality of strips, receiving second data of a second strip in a second stripe, wherein the second strip comprises a second plurality of strips, wherein a first logical address of the first data is the same as a second logical address of the second data, and generating a record indicating that the first data reaches the storage node before the second data.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: October 3, 2023
    Assignee: HUAWEI CLOUD COMPUTING TECHNOLGOIES CO., LTD.
    Inventors: Mingchang Wei, Daohui Wang, Chi Song, Rong Rao
  • Patent number: 11768609
    Abstract: Techniques are described for managing access of executing programs to non-local block data storage. In some situations, a block data storage service uses multiple server storage systems to reliably store network-accessible block data storage volumes that may be used by programs executing on other physical computing systems. A group of multiple server block data storage systems that store block data volumes may in some situations be co-located at a data center, and programs that use volumes stored there may execute on other physical computing systems at that data center. If a program using a volume becomes unavailable, another program (e.g., another copy of the same program) may in some situations obtain access to and continue to use the same volume, such as in an automatic manner in some such situations.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: September 26, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Roland Paterson-Jones, Peter N. DeSantis, Atle Normann Jorgensen, Matthew S. Garman, Tate Andrew Certain
  • Patent number: 11755209
    Abstract: An error detection and correction method for a flash memory includes: a setting step, setting selection information to select a first error detection and correction function for performing 1-bit error detection and correction or a second error detection and correction function for performing multiple-bit error detection and correction; and an executing step, performing the first error detection and correction function or the second error detection and correction function based on the selection information during a read operation or a write operation.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: September 12, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Takamichi Kasai, Fujimi Kaneko