Abstract: A method for forming a field oxide of a semiconductor device is disclosed, which takes advantage of wet oxidation at an early stage of field oxidation to prevent the ungrowth of field oxide and dry oxidation at a later stage of field oxidation to make the slope of field oxide positive, thereby improving the production yield and the reliability of semiconductor device.

Abstract: Disclosed is a method of manufacturing a semiconductor device having a reliable element isolation insulating film on an SOI substrate having an SOI layer. That is, the step of forming a semiconductor device on an SOI substrate includes the steps of sequentially depositing a silicon oxide film and an insulating film resistant to oxidation on the surface of the SOI layer of the SOI substrate to form a stacked film, etching the stacked film into a predetermined pattern shape to expose the SOI layer, selectively forming a thin silicon layer on the exposed SOI layer, and selectively thermally oxidizing the thin silicon layer and the exposed SOI layer by using the stacked film as a thermal oxidization mask. In the thermal oxidization step, all the thin silicon layer and the exposed SOI layer are thermally oxidized to be converted into an element isolation insulating film, and the element isolation insulating film is formed in contact with a buried oxide film below the region.

Abstract: A method of fabricating a ferroelectric capacitor structure by sequentially depositing a bottom electrode layer, a ferroelectric layer and a top electrode layer on a base structure, optionally with deposition of a layer of a conductive barrier material beneath the bottom electrode layer, to form a capacitor precursor structure, and planarizing the capacitor precursor structure by chemical mechanical polishing to yield the ferroelectric capacitor structure, e.g., a stack capacitor or trench capacitor. The process is carried out without dry etching of the electrode layers or dry etching of the ferroelectric layer, to yield ferroelectric capacitors having a very small feature size, as for example between 0.10 and 0.20 .mu.m.

Abstract: A method for forming N- and P-channel transistors having shallow junctions in an integrated circuit device is described. A semiconductor substrate is provided having active regions separated from one another by isolation regions wherein there is a N-channel active region and a P-channel active region and wherein gate electrodes and associated lightly doped source and drain regions have been formed in each of the active regions. A layer of borosilicate glass is deposited overlying the semiconductor substrate. A photoresist mask is formed over the P-channel active region. The borosilicate glass layer is etched away where it is not covered by the photoresist mask thereby leaving the borosilicate glass layer only overlying the P-channel region. The photoresist mask is removed. A layer of phosphosilicate glass is deposited overlying the semiconductor substrate.