Abstract: A direct bonding method for infrared focal plane arrays, includes steps of depositing a thin adhesion layer on infrared radiation detecting material, removing a portion of the thin adhesion layer with a chemical-mechanical polishing process, forming a bonding layer at a bonding interface, and bonding the infrared radiation detecting material to a silicon wafer with the thin adhesion layer as a bonding layer. The thin adhesion layer may include SiOx, where x ranges between 1.0 and 2.0. The thickness of the thin adhesion layer to form the bonding layer is 500 angstrom or less.

Abstract: A semiconductor device includes: a first stack structure; a second stack structure; a slit insulating layer located between the first stack structure and the second stack structure, the slit insulating layer extending in a first direction; a conductive plug located between the first stack structure and the second stack structure, the conductive plug including a first protrusion part protruding to the inside of the slit insulating layer; and an insulating spacer surrounding a sidewall of the conductive plug.

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

Abstract: The embodiments provide a process for easily producing an electrode having low resistance, easily subjected to post-process and hardly impairing the device; and also provide, as its application, a production process for a photoelectric conversion device. The process comprises the steps of: coating a hydrophobic substrate directly with a dispersion of metal nanomaterial, to form a metal nanomaterial layer, coating the surface of the metal nanomaterial layer with a dispersion of carbon material, to form a carbon material layer and thereby to form an electrode layer comprising a laminate of the metal nanomaterial layer and the carbon material layer, pressing the carbon material layer onto a hydrophilic substrate so that the surface of the carbon material layer may be directly fixed on the hydrophilic substrate, and peeling away the hydrophobic substrate so as to transfer the electrode layer onto the hydrophilic substrate.

Abstract: A solid-state imaging element including: a photoelectric conversion layer, a first electrode and a second electrode opposed to each other with the photoelectric conversion layer interposed therebetween, a semiconductor layer provided between the first electrode and the photoelectric conversion layer, an accumulation electrode opposed to the photoelectric conversion layer with the semiconductor layer interposed therebetween, an insulating film provided between the accumulation electrode and the semiconductor layer, and a barrier layer provided between the semiconductor layer and the photoelectric conversion layer.

Abstract: An SOI semiconductor structure, including a substrate layer formed on a back side and a semiconductor layer of a second conductivity type formed on a front side, an insulating layer being disposed between the substrate layer and the semiconductor layer, a three-dimensional Hall sensor structure having a sensor region made up of a monolithic semiconductor body being formed in the semiconductor layer, and the semiconductor body extending from an underside up to the front side, at least three first metallic terminal contacts being formed on the upper side, and at least three second metallic terminal contacts being formed on the underside, the first terminal contacts being offset with respect to the second terminal contacts in a projection perpendicular to the front side, each first terminal contact and each second terminal contact being formed in each case on a highly doped semiconductor contact region of a second conductivity type.

Abstract: A microelectronic package may include stacked microelectronic dice, wherein a first microelectronic die is attached to a microelectronic substrate, and a second microelectronic die is stacked over at least a portion of the first microelectronic die, wherein the microelectronic substrate includes a plurality of pillars extending therefrom, wherein the second microelectronic die includes a plurality of pillars extending therefrom in a mirror-image configuration to the plurality of microelectronic substrate pillars, and wherein the second microelectronic die pillars are attached to microelectronic substrate pillars with an attachment material.

Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. The air gap has a cross-section of substantially bottle shape with a flat top. A porous dielectric layer is disposed over the substrate, sealing the flat top of the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.

Abstract: According to an embodiment of the invention, the organic EL device (100) comprises: an element substrate (20) having a substrate (1) and a plurality of organic EL elements (3) supported by the substrate; a thin film encapsulation structure (10) formed above the plurality of organic EL elements and having at least one compound layered body (10S) constituted by a first inorganic barrier layer (12), an organic barrier layer (14) in contact with the upper surface of the first inorganic barrier layer and having a plurality of solid sections spread out discretely, and a second inorganic barrier layer (16) in contact with the upper surface of the first inorganic barrier layer and the upper surfaces of the plurality of solid sections of the organic barrier layer; an organic planarization layer (42) provided above the thin film encapsulation structure and formed from a photosensitive resin; and a touch sensor layer (50) disposed above the organic planarization layer.

Abstract: A method of making a semiconductor device includes: providing a substrate; forming an insulating layer on the substrate; forming a first trench in the insulating layer; forming a first semiconductor layer in the first trench; and removing a portion of the insulating layer to expose the first semiconductor layer.

Abstract: An ink used in forming a functional layer of a self-luminous element by a printing method, the ink including a functional material and a mixed solvent. The mixed solvent includes solvents each having different vapor pressures. The functional material is dissolved or dispersed in the mixed solvent. A solvent that has a lowest vapor pressure among the solvents has a viscosity of at least 53 mPa·s, and a viscosity of the mixed solvent is 15 mPa·s or less.

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.

Abstract: A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a second conductive line disposed adjacent to the first conductive line, surrounded by the dielectric layer and extended parallel to the first conductive line; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via substantially parallel to the first surface of the substrate, wherein the cross section of the conductive via is at least partially protruded from the first conductive line towards the second conductive line. Further, a method of manufacturing the semiconductor structure is also disclosed.

Abstract: IC structures that include transmission line structures to be integrated with III-N devices are disclosed. An example transmission line structure includes a transmission line of an electrically conductive material provided above a stack of a III-N semiconductor material and a polarization material. The transmission line structure further includes means for reducing electromagnetic coupling between the line and charge carriers present below the interface of the polarization material and the III-N semiconductor material. In some embodiments, said means include a shield material of a metal or a doped semiconductor provided over portions of the polarization material that are under the transmission line. In other embodiments, said means include dopant atoms implanted into the portions of the polarization material that are under the transmission line, and into at least an upper portion of the III-N semiconductor material under such portions of the polarization material.

Abstract: In a semiconductor device including a transistor including an oxide semiconductor film and a protective film over the transistor, an oxide insulating film containing oxygen in excess of the stoichiometric composition is formed as the protective film under the following conditions: a substrate placed in a treatment chamber evacuated to a vacuum level is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C.; a source gas is introduced into the treatment chamber so that the pressure in the treatment chamber is set to be higher than or equal to 100 Pa and lower than or equal to 250 Pa; and a high-frequency power higher than or equal to 0.17 W/cm2 and lower than or equal to 0.5 W/cm2 is supplied to an electrode provided in the treatment chamber.

Abstract: A display device, includes a substrate having at least two colored subpixels and a white subpixel separately arranged thereon; a first anode having a first thickness at each of the colored subpixels on the substrate; a second anode, having a thickness smaller than the first thickness, at the white subpixel on the substrate; an organic stack comprising a first stack having a first blue emission layer, a second stack having a second blue emission layer, and a third stack having at least one of emission layers having a longer wavelength than the blue emission layers, which are provided in sequence on the first anode in the colored subpixel and the second anode in the white subpixel; a cathode over the organic stack; and a compensation pattern between the second anode and the substrate.

Abstract: One or more embodiments are directed to establishing electrical connections through silicon wafers with low resistance and high density, while at the same time maintaining processability for further fabrication. Such connections through silicon wafers enable low resistance connections from the top side of a silicon wafer to the bottom side of the silicon wafer.

Abstract: A method for manufacturing three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is formed and bonded to a first IC die by a first bonding structure. A third IC die is formed and bonded to the second IC die by a second bonding structure. The second bonding structure is formed between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. In some further embodiments, the second bonding structure is formed by forming conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.