Abstract: The driver circuit includes a pull-up network having a first pull-up transistor controlled by a data signal, a second pull-up transistor coupled between the first pull-up transistor and a first power supply voltage, and a third pull-up transistor coupled in parallel with the second pull-up transistor. The third pull-up transistor is configured to turn on for at least one clock cycle responsive to a change in the logic level of the data signal being detected.

Abstract: Methods and devices to mitigate de-biasing caused by an undesired gate induced drain body leakage current in FET switch stacks are disclosed. The devices utilize diode stacks to generate discharge paths for the undesired current. The disclosed teachings are applicable to both shunt and series implementations of FET switch stacks.

Abstract: An LDO regulator includes an error amplifier, a power transistor, a monitoring circuit and/or an adaptive pole adjusting circuit (APAC). The error amplifier compares a reference voltage and a feedback voltage to generate a first error voltage based on the comparison. The power transistor including a gate coupled to an output terminal of the buffer, regulates an input voltage based on a second error voltage which is generated based on the first error voltage to provide an output voltage to an output node. The monitoring circuit, connected to the output terminal of the buffer in parallel with the power transistor, generates a control voltage associated with a load current. The APAC, connected between the output terminal of the error amplifier and the ground voltage, selectively connects an adjusting capacitor between the output terminal of the error amplifier and the ground voltage in response to the control voltage.

Abstract: A multi-frequency uniformization carrier wave slope random distribution pulse width modulation method, includes: (1) selecting a required random carrier wave sequence and a modulating wave, and after the two are compared, generating a switch device drive signal for pulse width modulation; (2) determining a multiple n of an equivalent carrier frequency f of the random carrier wave sequence, and selecting a main circuit topology; and (3) inputting the switch device drive signal generated in (1) into the main circuit topology of (2) to perform multi-frequency uniformization carrier wave slope random distribution pulse width modulation. The disclosure can improve a frequency domain distribution bandwidth of a harmonic wave without changing the mean and variance of a random carrier wave sequence, and realizes uniform distribution of carrier waves and multiple harmonic peaks near a doubled frequency of the carrier waves in a wider frequency domain.

Abstract: A semiconductor device includes an inverter circuit having a first switching element and a second switching element, a first control circuit, a second control circuit, and a limiting unit. The first switching element is supplied with a power supply voltage. The second switching element includes a first terminal connected to the first switching element, a second terminal connected to ground, and a control terminal. The first control circuit controls the first switching element. The second control circuit controls the second switching element. The limiting unit reduces fluctuation in voltage between the second terminal and the control terminal based on voltage fluctuation at the second terminal of the second switching element.

Abstract: A charge pump structure is disclosed. In an embodiment a regulated charge pump structure includes an output terminal configured to provide a regulated output voltage, a first charge pump configured to generate the output voltage as a function of an input supply voltage and a control circuit configured to limit a level of the output voltage and to generate a control voltage, wherein the level of the output voltage is controlled by the control voltage such that the output voltage does not exceed a threshold value.

Abstract: A circuit includes first and second transistors, an adaptive bias current source circuit, and an adaptive resistance circuit. The first transistor has a control terminal and first and second current terminals. The control terminal of the first transistor being a first input to the circuit. The second transistor has a control terminal and first and second current terminals, and the control terminal of the second transistor is a second input to the circuit. The first and second inputs are differential inputs to the circuit. The adaptive bias current source circuit is coupled to the second current terminal of the first transistor. The adaptive resistance circuit is coupled between the second current terminal of the second transistor and the adaptive bias current source circuit.

Abstract: A method of frequency doubling includes receiving a first clock that has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase; outputting a second clock using a multiplexer by selecting one of the first phase and the second phase of the first clock in accordance with a third clock; delaying the second clock into a fourth clock using a recirculating delay circuit; and using a divide-by-two circuit to output the third clock in accordance with the fourth clock.

Abstract: Provided is a semiconductor device including a normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode, a fourth electrode, and a second control electrode, a first capacitor having a first end and a second end, a Zener diode having a first anode and a first cathode, a first resistor having a third end and a fourth end, a first diode having a second anode and a second cathode, a second resistor having a fifth end and a sixth end, a second diode having a third anode and a third cathode, and a second capacitor having a seventh end and an eighth end.

Abstract: A device for switching a high-voltage source, comprising: a plurality of switching devices coupled in series starting from a first switching device and ending in a last switching device, said device enabling coupling of said high-voltage source with at least a selected one of said switching devices; a voltage limiter coupled with said switching devices; and a switching time synchronizer; wherein said first switching device is configured to directly receive a control signal for changing a switching state of said device, said first switching device is configured to facilitate a cascaded transition of switching states in successive said switching devices in said series, where said switching time synchronizer is configured to synchronize a time at which transitions to said switching states of successive said switching devices take effect, and said voltage limiter is configured to limit overvoltage conditions to said switching devices during said transitions.

Abstract: Various embodiments include a switching device for disconnecting a current path in a DC supply system, said current path comprising inductances at the source end and the load end, the switching device comprising: two series-connected switching modules; wherein each of the series-connected switching modules comprises a controllable semiconductor switching element and a series circuit; the series circuit including a resistor and a capacitor connected in parallel to the controllable semiconductor switching element.

Abstract: Both before and after a surprise clock stop, the apparatus and method of various embodiments supplies a stable and continuous clock to a memory module with a unique arrangement of circuit components, including a clock detector circuit, a clock-smoothing circuit, and one or more PLLs. Upon detection of a stopped host clock, a first PLL seamlessly switches to an alternate reference clock from an on-board crystal oscillator. A clock smoothing circuit allows the first PLL to maintain a steady phase and frequency without inducing glitches or period excursions greater than the natural jitter of the locked PLL; one or more optional downstream PLLs may drive additional clock domains.

Abstract: A single-pole double-throw switch includes switching units which are set between a first port and a second port and between the first port and a third port, respectively, and are configured to perform complementarily. The each switching unit includes an antenna port, a circuit port, a transmission line configured to couple them, and a switching element connected between the transmission line and a ground. The switching element includes a parallel circuit including a transistor and an inductor connected in parallel, and a capacitor connected in series with the parallel circuit. The transmission line has a characteristic impedance different from a impedance seen inside the switching unit from the antenna port and a impedance seen inside the switching unit from the circuit port.

Abstract: The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a first latch unit for transmitting data of the input terminal and latching the data under control of a clock signal; a second latch unit for latching data of the output terminal and inversely transmitting the data latched by the first latch unit under control of a clock signal; and an output driving unit for inverting and outputting the data received from the second latch unit; wherein the second latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.

Abstract: A locked-loop circuit includes phase synchronization circuitry to synchronize a DCO clock phase to a reference clock phase. Sampling circuitry sequentially samples the reference clock with each of N sampling clocks having offset phases, a first one of the N sampling clocks comprising a master sampling clock. Edge detection logic accumulates phase information from the multiple sampling clocks and determines, based on the accumulated phase information, whether any of the sampling clocks other than the master sampling clock correspond to edge detection signals that occurred early with respect to a rising edge of the master sampling clock. Index logic generates index values for any of the determined early edge detection signals. The index logic transfers the generated index values to a master phase transfer logic unit. Phase adjust logic adjusts the master clock phase based on a selected one of the generated index values.

Abstract: A slew rate control circuit is disclosed. The slew rate control circuit includes an input port to receive an input signal, a transmitter to transmit the input signal to an output port and an impedance control circuit coupled between the transmitter and the output port. The impedance control circuit has an adjustable impedance that is configured to be adjusted during a rise and a fall of the input signal using a trim code and an one shot pulse.

Abstract: A scan flip-flop includes a multiplexer, a first latch, a second latch, an output buffer and a clock buffer. The multiplexer selects one of a data input signal and a scan input signal based on an operation mode. The first latch latches an output of the multiplexer. The second latch latches an output of the first latch. The output buffer generates an output signal based on an output of the second latch. The clock buffer generates a first clock signal and a second clock signal that control operation of the first latch and the second latch. The first latch, the second latch, and the clock buffer are sequentially arranged along a first direction. A first clock line supplying the first clock signal and a second clock line supplying the second clock signal have a cross couple connection.

Abstract: Embodiments relate to a phase interpolator cell. The phase interpolator cell includes a multiplexer configured to select between a first pull-up network and a second pull-up network. The first pull-up network includes a first pull-up transistor controlled by a first clock signal and is connected between a first input of the multiplexer and a first power supply. The second pull-up network includes a second pull-up transistor controlled by a second clock signal and is connected between a second input of the multiplexer and the first power supply.

Abstract: A wireless power transmitting and charging system is disclosed. A method for operating a power transmitter of the wireless power transmitting and charging system comprises the steps of: maintaining a ping value table where ping signal conditions are mapped according to the height of a power receiver; recognizing the power receiver by varying a ping signal according to the ping signal conditions recorded in the ping value table; and controlling a charging mode according to a message received from the power receiver.

Abstract: A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.