Abstract: A metal-dielectric bonding method includes providing a first semiconductor structure including a first semiconductor layer, a first dielectric layer on the first semiconductor layer, and a first metal layer on the first dielectric layer, where the first metal layer has a metal bonding surface facing away from the first semiconductor layer; planarizing the metal bonding surface; applying a plasma treatment on the metal bonding surface; providing a second semiconductor structure including a second semiconductor layer, and a second dielectric layer on the second semiconductor layer, where the second dielectric layer has a dielectric bonding surface facing away from the second semiconductor layer; planarizing the dielectric bonding surface; applying a plasma treatment on the dielectric bonding surface; and bonding the first semiconductor structure with the second semiconductor structure by bonding the metal bonding surface with the dielectric bonding surface.

Abstract: The present technology relates to a solid-state imaging element, a solid-state imaging element package, and electronic equipment that can suppress occurrence of flares. The solid-state imaging element includes an effective pixel region and a peripheral circuit region. The effective pixel region includes a plurality of pixels arranged two-dimensionally in a matrix pattern. The peripheral circuit region is provided around the effective pixel region. The effective pixel region has a pixel-to-pixel light-shielding film formed at boundary portions between the pixels. In a region on a substrate where a rib structure is formed within the peripheral circuit region, no light-shielding film is formed in the same layer as the pixel-to-pixel light-shielding film. The present technology is applicable, for example, to a solid-state imaging element package including a cover glass that protects a light-receiving surface of the solid-state imaging element.

Abstract: The embodiment relates to a packaging substrate and a semiconductor device, including an element unit including a semiconductor element; and a packaging substrate electrically connected to the element unit; and it applies a glass substrate as a core of the packaging substrate, thereby can significantly improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a motherboard to be closer to each other so that electrical signals are transmitted through as short a path as possible. Therefore, it can significantly improve electrical properties such a signal transmission rate, substantially prevent generating of parasitic element, and simplify a process of treatment for an insulating layer, and thus provides a packaging substrate applicable to a high-speed circuit.

Abstract: An image sensor includes a sensor pixel. The sensor pixel includes a first transistor coupled between a first power source and a first node, where the first transistor is turned on in response to a first control signal, a light-sensing element coupled between the first node and a second power source, where the light-sensing element generates photocharges in response to incident light, a storage capacitor coupled in parallel to the light-sensing element between the first node and the second power source, and an amplifier including a plurality of transistors coupled in series between the first power source and an output line, where the amplifier outputs a sensing signal corresponding to a voltage of the first node in response to a first driving signal.

Abstract: An apparatus for forming a package structure is provided. The apparatus includes a processing chamber for bonding a first package component and a second package component. The apparatus also includes a bonding head disposed in the processing chamber. The bonding head includes a plurality of vacuum tubes communicating with a plurality of vacuum devices. The apparatus further includes a nozzle connected to the bonding head and configured to hold the second package component. The nozzle includes a plurality of first holes that overlap the vacuum tubes. The nozzle also includes a plurality of second holes offset from the first holes, wherein the second holes overlap at least two edges of the second package component. In addition, the apparatus includes a chuck table disposed in the processing chamber, and the chuck table is configured to hold and heat the first package component.

Abstract: This patent application relates to methods and apparatus for temperature modification within a stack of microelectronic devices for mutual collective bonding of the microelectronic devices, and to related substrates and assemblies.

Abstract: A method for producing a connection between component parts and a component made of component parts are disclosed. In an embodiment, a includes providing a first component part having a first exposed insulation layer and a second component part having a second exposed insulation layer, wherein each of the insulation layers has at least one opening, joining together the first and second component parts such that the opening of the first insulation layer and the opening of the second insulation layer overlap in top view, wherein an Au layer and a Sn layer are arranged one above the other in at least one of the openings and melting the Au layer and the Sn layer to form an AuSn alloy, wherein the AuSn alloy forms a through-via after cooling electrically conductively connecting the first component part to the second component part.

Abstract: An epitaxial structure includes a composite base unit and an emitter unit. The composite base unit includes a first base layer and a second base layer formed on the first base layer. The first base layer is made of a material of InxGa(1-x)As(1-y)Ny, in which 0<x?0.2, and 0?y?0.035, and when y is not 0, x=3y. The second base layer is made of a material InmGa(1-m)As, in which 0.03?m?0.2. The emitter unit is formed on the second base layer 12 opposite to the first base layer 11, and is made of an indium gallium phosphide-based material. A transistor including the epitaxial structure is also disclosed.

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

Abstract: One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.

Abstract: A method and apparatus for wafer bonding. The method includes that, a first position parameter of a first alignment mark on a first wafer is determined by using a optical beam; a second position parameter of a second alignment mark on a second wafer is determined with the optical beam, the optical beam has a property of transmitting through a wafer; a relative position between the first wafer and the second wafer is adjusted with the optical beam according to the first position parameter and the second position parameter until the relative position between the first alignment mark and the second alignment mark satisfies a predetermined bonding condition; and the first wafer is bonded to the second wafer.

Abstract: A semiconductor packaging method and a semiconductor package device are provided. The packaging method includes providing a chip. The chip includes a chip substrate having a front surface and a back surface, where the front surface includes a photosensitive region; a plurality of pads disposed at the front surface of the chip substrate and around the photosensitive region, where the chip substrate contains a through-hole formed from the back surface of the chip substrate, and the plurality of pads are exposed from the through-hole; and a transparent protection layer over the front surface of the chip substrate, where the transparent protection layer covers the photosensitive region and the plurality of pads. The packaging method also includes electrically connecting each pad of the plurality of pads to a circuit board through a corresponding metal rewiring layer in the through-hole.

Abstract: An integrated circuit (IC) package comprises a substrate having an outer portion close to the perimeter of the substrate, an inner portion surrounded by the outer portion, and an upper surface incorporating a wiring layer for the bonding of a semiconducting die (e.g., via its bottom face). The IC package includes a metallic or otherwise thermally conductive heat spreader thermally bonded on an inner surface of a boss on its bottom side to the top surface of the semiconducting die, and extending on its top surface to the edges of the substrate to maximize heat dissipation from the die. The boss extends toward the semiconducting die and is thermally coupled to the top face of the semiconducting die.

Abstract: An electronic component includes a first substrate having a substantially quadrangular planar shape and having a first surface and a second surface, the first surface and the second surface being opposite to each other, an element disposed on the first surface, four first terminals located adjacent to four corners on the second surface, respectively, and a second terminal located between the first terminals at respective ends of each of two sides opposite to each other of the second surface, an area of the second terminal being smaller than an area of each of the first terminals at the respective ends of each of the two sides, a width of the second terminal in an extension direction of each of the two sides being equal to or less than a width of each of the first terminals at the respective ends of each of the two sides in the extension direction.

Abstract: The invention relates to a non-volatile resistive random access memory (ReRAM), a non-volatile ReRAM composition and to a method for manufacturing a non-volatile non-volatile ReRAM. The ReRAM includes a first electrode, a second electrode and a resistive switching/active layer which is located between the first and second electrodes. The switching layer contains chitosan and aluminium doped/incorporated zinc oxide. The switching/active layer may be configured to perform a switching operation according to an applied voltage. The switching/active layer may be in the form of a film. The switching/active layer may be coated/applied onto the first electrode and the second electrode may be placed/applied/provided over the switching/active layer such that the switching/active layer is located/wedged in-between the two electrodes.

Abstract: A magnetoresistive stack includes a fixed magnetic region, one or more dielectric layers disposed on and in contact with the fixed magnetic region, and a free magnetic region disposed above the one or mom dielectric layers. The fixed magnetic region may include a first ferromagnetic region, a coupling layer, a second ferromagnetic region, a transition layer disposed, a reference layer, and at least one interfacial layer disposed above the second ferromagnetic region. Another interfacial layer may be disposed between the one or more dielectric layers and the free magnetic region.

Abstract: Embodiments of methods and apparatus for reducing warpage of a substrate are provided herein. In some embodiments, a method for reducing warpage of a substrate includes: applying an epoxy mold over a plurality of dies on the substrate in a dispenser tool; placing the substrate on a pedestal in a curing chamber, wherein the substrate has an expected post-cure deflection in a first direction; inducing a curvature on the substrate in a direction opposite the first direction; and curing the substrate by heating the substrate in the curing chamber.

Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of gate strips, each gate strip is a gate terminal of a transistor; forming a plurality of first contact vias connected to a part of the gate strips; forming a plurality of first metal strips above the plurality of gate strips; connecting one of the first metal strips to one of the first contact vias; forming a plurality of second metal strips above the plurality of first metal strips, wherein the plurality of second metal strips are co-planar, each second metal strip and one of the first metal strips are crisscrossed from top view; a length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one of the first metal strips is smaller than two and a half times as the length between two adjacent gate strips.

Abstract: A quantum dot light emitting diode and a method for fabricating the same. The quantum dot light emitting diode includes: a substrate, a bottom electrode, a light-emitting function layer, and a top electrode. A functional layer is formed by the bottom electrode, the light-emitting function layer, and the top electrode; and an outer surface of the functional layer is provided with a first protective layer. The first protective layer is made from a fluoro-acrylate copolymer, which has hydrophobicity, good light transmittance, flexibility, and heat dissipation, and can effectively prevent moisture and oxygen from penetrating into an internal structure of the quantum dot light emitting diode, thereby having a good protection effect, and in the meanwhile, the quantum dot light emitting diode can dissipate heat timely, which is beneficial for the device to keep its performance, improve light-emitting efficiency, and the service life.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes source/drain structures on opposite sides of the gate structure. The semiconductor structure also includes a dielectric layer over the gate structure and the source/drain structures. The semiconductor structure also includes a via plug passing through the dielectric layer and including a first group IV element. The dielectric layer includes a second group IV element, a first compound, and a second compound, and the second compound includes elements in the first compound and the first group IV element.