Abstract: An inexpensive method and means for generating high power envelope-modulated radio frequency signals is disclosed. Embodiments provide EER amplification and separate modulation of information encoded as phase angle and as amplitude. An envelope modulated signal generation apparatus comprising a source of carrier signal, a source of a binary data stream, a pulse deletion logic and a current switch is disclosed.

Abstract: The present invention, generally speaking, provides for bandwidth switching of a PLL in a simple, effective manner. In accordance with one embodiment, a phase lock loop includes a controlled oscillator responsive to a control voltage for producing an output signal of some output frequency; a comparator responsive to a feedback signal derived from the output signal and to a reference signal for producing at least one error signal; a charge pump circuit including multiple pairs of unidirectional current sources (or, alternatively, multiple bidirectional current sources); a control circuit responsive to a control signal for activating one or more pairs of unidirectional current sources, at the same time deactivating one or more pairs of unidirectional current sources; and a loop filter responsive to the multiple pairs of unidirectional current sources for producing the control voltage governing the output frequency.

Abstract: A detector circuit for determining whether synchronization lock has been optimally achieved in feedback-type control systems. The detector circuit evaluates an error signal developed by a phase/frequency detector and compares the absolute magnitude of the error signal to a first threshold signal corresponding to a magnitude metric. When the value of the error signal is less than the magnitude threshold value, an event signal initiates a time interval counter which continues counting so long as the error signal remains below the magnitude threshold value. The time interval counter continues until it counts to a second threshold value corresponding to a timing metric. At this point, synchronization lock is declared.

Abstract: A precise programmable duty cycle generator employs multiple duty cycle generators connected in series to provide multiple duty cycle tap point outputs, each with a known and precise value of a duty cycle from a source input signal having any duty cycle. The present invention transforms an incoming signal's duty cycle to a known value by a first programmable duty cycle generator, and then applies the output of the first programmable duty cycle generator to a second programmable duty cycle generator which provides multiple duty cycle tap point outputs, each having a different known value of a precise duty cycle.

Abstract: A precision oven-controlled crystal oscillator (OCXO) uses an adjustment feedback signal that, when mixed with a reference signal from a stable reference oscillator, accurately controls the generation of an output signal from a voltage controlled crystal oscillator (VCXO). An OCXO according to the invention has high stability and high accuracy. The digital OXCO can be manufactured at low cost, and is particularly beneficial for Code Division Multiple Access (CDMA) base station applications in cellular communication networks an the like.

Abstract: In an electronic circuit supplied from supply terminals, a terminal in the circuit being biased to a voltage between the supply terminal voltages, connections from power supply terminals are made via current generator means. The circuit is preferably an RF, balanced and/or oscillator circuit. The current generator means are preferably controllable current generators, preferably controlled by an AGC, or a common mode or differential voltage control circuit. Preferably, the controllable current generators comprise a FET or are substantially constituted by each one MOS-FET. A balanced, common-base, low-voltage Pierce crystal oscillator with two transistors and four to six current generator means is disclosed.

Abstract: Method for accounting for factors (such as temperature) causing systematic errors (time-varying or constant) in a clock, such as a clock used in a ranging receiver (for use with a positioning system such as the Global Positioning System), and a corresponding clock system (including a clock and a filter such as a Kalman filter) for providing clock time and error, used for example in a ranging receiver. The invention adds new state vector components to account for systematic error. The process update equation used in the navigation solution is accordingly extended to include the additional components of the state vector.

Abstract: A clock recovery circuit for recovering clock signals from one of a plurality of input reference signals, includes an acquisition phase locked loop (PLL) for each input. The acquisition PLL having phase comparator for comparing the phase of an input signal to a feedback signal, and first and second digital controlled oscillators (DCOs) receiving an input from the phase comparator. The first DCO of the acquisition PLL is in a feedback loop to supply an input to the phase comparator and the second DCO of the acquisition PLL has a control input to introduce a phase offset therein relative to said the DCO of the acquisition PLL and provides an output for the acquisition PLL. An output PLL has a phase comparator selectively connectable to the output of each of the acquisition PLLs. The output PLL has a first DCO providing an output for the circuit and a second DCO in a feedback loop providing a feedback signal to the phase comparator of the output PLL.

Abstract: The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.

Abstract: Physics package apparatus for a cell type atomic clock includes a cell structure having a central plate sandwiched between top and bottom plates. The central plate has a central interior aperture which together with the top and bottom plates forms an internal cavity for containment of an active vapor. The central plate includes a reservoir for holding a source of the active vapor, and a channel connecting the reservoir with the internal cavity. A heater is provided on the underside of the bottom plate for heating the vapor. The plates are batch processed on respective wafers which are subsequently joined together and cut into individual cell structures.

Abstract: The present invention provides a phase locked loop (10) for generating a variable output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the variable output frequency signal in response to a tune signal. A feedback frequency divider (16) coupled to the controlled oscillator (14) is operable to generate a divided frequency signal from the variable output frequency signal. A phase detector (18) generates an error signal representing a difference between a reference frequency signal and the divided frequency signal. A sample and hold circuit (22) is activable in response to a gating signal (20) derived from the reference frequency, to sample the error signal and generate a sampled signal. A loop filter (12) filters the sampled signal and generates the tune signal.

Abstract: A VCO for a PLL may include a ring oscillator having a power supply controlled in response to the VCO's control voltage input and an inverter having an input coupled to the ring oscillator's output and also supplied with a power supply controlled by the control voltage input. Together, the output of the ring oscillator and the output of the inverter may closely approximate a differential signal. The VCO may include an amplifier for amplifying a differential input to an output in the voltage domain of the system including the PLL. The output of the ring oscillator may be used as an input to the amplifier, and the output of the inverter may be used as the other input. The power supply terminals of the ring oscillator and the inverter may be coupled to outputs of a current mirror. In one implementation, the current mirror may not be cascoded.

Abstract: A fast lock/self-tuning VCO based PLL integrated circuit (10) adapted for implementation in wireless communication systems requiring a high transfer data rate. The present invention is preferably implemented using and RFSiGe or a CMOS process in a WDCMA chipset, and can be used in other systems such as GSM and EDGE. The present invention utilizes the content of a divider (24) as a monitor of the lock condition of the PLL (10), permitting the fast-tuning of the VCO (14) to almost the final frequency using a controller (22) and a coarse DAC (20).

Abstract: A method and apparatus for frequency shift-keying (FSK) demodulation includes processing that begins by generating a charge signal, a data acquisition signal, and a reset signal from an I component and a Q component of an FSK modulated signal. The processing continues by generating a delta frequency signal based on the charge signal, the data acquisition signal, and the reset signal. The delta frequency signal is representative of the frequency difference used within the FSK modulation to indicate a logic 1 and a logic 0. The processing then continues by demodulating the delta frequency signal to recapture a stream of data.

Abstract: A PLL circuit comprises a circuit which issues an alarm when fluctuation of the potential of a DC power source connected to the PLL circuit exceeds a predefined range. A first potential generation circuit generates a first potential higher than a steady-state potential of the DC power source. A second potential generation circuit generates a second potential lower than the steady-state potential of the DC power source. A first comparator circuit compares a local maximum potential of the DC power source with the first potential. A second comparator circuit compares a local minimum potential of the DC power source with the second potential. A supply circuit supplies a drive voltage to an alarm issuer, in a case where the local maximum potential is higher than the first potential, and/or the local minimum potential is lower than the second potential, based on the comparison results.

Abstract: An oscillator having multi-phase complementary outputs comprises a first plurality of single ended amplifiers connected in series to form an input and an output and a second plurality of single ended amplifiers connected in series to form an input and an output. The first and second plurality have the same odd number of amplifiers, A first feedback path connects the output to the input of the first plurality of amplifiers to establish oscillations in the first plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the first plurality. A second feedback path connects the output to the input of the second plurality of amplifiers to establish oscillations in the second plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the second plurality.

Abstract: A varactor folding technique reduces noise in controllable electronic oscillators through the use of a series of varactors having relatively small capacitance. A folding circuit provides control signals to the varactors in a sequential manner to provide a relatively smooth change in the total capacitance of the oscillator. Consequently, effective control of the oscillator is achieved with accompanying reductions in oscillator noise such as flicker noise.

Abstract: A frequency synthesizer is provided with a prescaler 2 and a counter 3, which output a signal having a frequency generated by frequency-dividing an output signal of a VCO 1; a reference frequency divider 5 for frequency-dividing a frequency of a reference signal of a reference signal source 4; a frequency adjusting meas 9 operated in such that a frequency error between the output signal of the counter 5 and the output signal of the reference frequency divider 5 is detected, and in response to this detection result, such a signal is outputted by which either a capacitor value or an inductor value employed in a resonant circuit of the VCO 1 is switched; and also a bias control means for applying an arbitrary voltage V1 to a control voltage terminal of the VCO 1 so as to bring an output signal of a charge pump 7 into a high impedance state when the frequency adjusting means 9 is operated.

Abstract: A pulse density modulator unit transforms an N-bit input signal representing an input value, into an output digital signal having a digital pulse density which is a linear function of the input value. The pulse density modulator unit includes a first pulse density modulator which produces a binary signal representing a multiplication factor as a pulse density. It further includes a combination module which receives the input signal, the binary signal from the first pulse density modulator and an offset control signal. The combination module produces a combined signal which, on average, represents the product of the input signal and the amplification control signal, offset by an amount dependent upon the offset control signal. A second pulse generator uses the combined signal to generate the output digital signal. The combination module may be a selector.

Abstract: Resuming the operation of a phase locked loop (PLL) that has entered a hang up status. The output of the PLL is examined to determine whether the output is stuck at either high or low logical value. The PLL is initialized if the output is stuck. Once initialized, the PLL may resume generating a desired output clock signal.