Patents Examined by David Foster
  • Patent number: 6147877
    Abstract: A device for transferring electric signals comprises a first unit having a bus and electrical and mechanical interconnections of this bus and a bus of another device at at least one side of the unit. A second unit has terminals electrically connected to the bus for external connection of the device to, and signal exchange with, electrical arrangements. The device further comprises two different carriers on which the bus unit and the terminal unit, respectively, are arranged, and members for releasable mechanical connection of the two carriers to each other, and adapted to allow separation of the terminal unit from the bus unit with maintained connection thereof to the bus unit of an adjacent device.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: November 14, 2000
    Assignee: Asea Brown Boveri AB
    Inventors: Lars Strandberg, Erki Kurttila
  • Patent number: 6147875
    Abstract: A circuit body 10 includes a main circuit body 12 having an inner circuit; a plurality of connector blocks 13, 14 integrally supported by the main circuit body 12 and directly connected to electric parts; and flexible legs 21a, 21b, 21c, 21d for supporting the plurality of connector blocks 13, 14 independently from the main circuit body 12 so that they can be freely moved in the direction perpendicular to the connecting direction of the electric parts.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: November 14, 2000
    Assignee: Yazaki Corporation
    Inventor: Toshimasa Yoshigi
  • Patent number: 6147870
    Abstract: A printed circuit assembly and method of making the same facilitates the attachment of high density modules onto a printed circuit board. In one embodiment, the high density modules are attached to the printed circuit board using an adhesive having a conductive material disposed within at least one via. In an alternate embodiment, an adhesive layer including a plurality of non-conductive "gauge particles" disposed within a non-conductive adhesive is used to attach the module to the printed circuit board. When the adhesive layer is disposed between a module and a printed circuit, individual gauge particles are interposed or sandwiched at various points between the layers such that the diameters of the particles control the layer separation throughout overlapping areas of thereof, thereby permitting careful control over layer separation.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: November 14, 2000
    Assignee: Honeywell International Inc.
    Inventor: Richard J. Pommer
  • Patent number: 6144560
    Abstract: A semiconductor device including bond pads disposed proximate an edge thereof, and an overcoat layer. The overcoat layer defines notches around each of the bond pads. The overcoat layer may be formed from a photoimageable material such as a photoimageable epoxy. The invention also includes an alignment device that secures the semiconductor device perpendicularly upon a carrier substrate. The alignment device includes intermediate conductive elements which correspond to the bond pads of the semiconductor device. Upon insertion of the semiconductor device into the alignment device, the notches facilitate alignment of the bond pads with their corresponding intermediate conductive elements. The intermediate conductive elements establish an electrical connection between the semiconductor device and the carrier substrate.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: November 7, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Walter L. Moden, Larry D. Kinsman
  • Patent number: 6144559
    Abstract: Disclosed is a process to manufacture an interposer which includes an interposer socket assembly to use in probing dense pad arrays that minimizes the associated extraneous pin loading and cross-talk caused by a probe tip. The process comprises the steps of: mounting a number of resistors onto a number of predetermined positions in a pad array on an interposer board; inserting a number of interposer pins of a pin socket into the pads of the pad array on the interposer board, wherein the ends of the interposer pins protrude through the interposer board; placing a solder preform around the ends of the interposer pins; and, heating the solder preforms in a solder re-flow oven to solder the interposer pins to the respective pads of the pad array.
    Type: Grant
    Filed: April 8, 1999
    Date of Patent: November 7, 2000
    Assignee: Agilent Technologies
    Inventors: Kenneth W Johnson, Thomas J Zamborelli, Larry Bartosch
  • Patent number: 6137691
    Abstract: A three dimensional composite circuit board includes a first, second, and third circuit boards and a molding material. The first, second and third circuit board have a plurality of plates which are each folded in order to form a separate cubic shape. The second circuit board has a volume smaller than a volume of the first circuit board so as to be accommodated in the first circuit board, and is coupled to the first circuit board. The third circuit board has a volume smaller than the volume of the second circuit board so as to be accommodated in the second circuit board, and is coupled to the second circuit board. The molding material coats electronic elements which are mounted in the first, second and third circuit boards and brazing portions of the electronic elements to shield the electromagnetic waves generated by the electronic elements.
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: October 24, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyung-Woo Jang
  • Patent number: 6137690
    Abstract: An electronic assembly (10) comprises one or more electronic components (18) having solder terminations (20), and a printed circuit substrate (12) having printed circuit traces (14, 16), wherein at least one of the solder terminations of the one or more electronic components (18) and the printed circuit traces (14, 16) of the printed circuit substrate (12) has a secondary finish produced by application of an electrolessly deposited nickel film (26) containing phosphorus which is further plated with gold (28). An indium-tin-lead solder paste (22) is utilized in a soldering process to attached the one or more electronics components (18) to the printed circuit traces (14,16) on the printed circuit board (12), such that the indium-tin-lead solder (22) provides improved solder joint integrity with the secondary finish. The electronic components (18) include semiconductor devices such as ball grid arrays (1000) and flip-chip integrated circuits (1010).
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: October 24, 2000
    Assignee: Motorola
    Inventors: Robert Thomas Carson, Arnold William Hogrefe, Frank Juskey
  • Patent number: 6134120
    Abstract: A board mount assembly. The assembly comprises a panel, a board mount and a circuit board. The panel is generally arranged in a plane. The board mount has an attachment portion operably connected to the panel and parallel thereto, and has a support portion extending from the first portion at a non-perpendicular angle relative to the plane of the panel. The circuit board has a first standoff engaged with the board mount.
    Type: Grant
    Filed: September 4, 1998
    Date of Patent: October 17, 2000
    Assignee: American Standard Inc.
    Inventors: Joe M. Baldwin, Dale C. Cotton, Bruce D. Smalling
  • Patent number: 6134117
    Abstract: A method for high resolution trimming of PCB components, such as capacitors, inductors, transmission lines, transformers, antennas, resistors, etc. The method includes drilling or milling the PCB to effect the electrical characteristics of the component. The actual component can be machined to reduce the size of the component, or electrical connections to the component can be severed. The method can be used to set the capacitance of a tuning capacitor for an oscillator circuit. The tuning capacitor is etched out of the conductive planes on opposing sides of the PCB. The dielectric substrate of the PCB acts as the dielectric for the capacitor. The conductive planes are also etched to define conductive traces and connection pads suitable for surface mounting and electrically connecting the various electrical components on the PCB. The area of the selectively etched capacitive plates has a capacitance that is predetermined.
    Type: Grant
    Filed: April 16, 1999
    Date of Patent: October 17, 2000
    Assignee: Delphi Technologies, Inc.
    Inventors: John David Funk, Paul John Dobosz
  • Patent number: 6130823
    Abstract: A stackable ball grid array module in which a chip select decoder is used to reduce the number of busses required for communication between modules. Additional modules may be added without requiring additional interconnect lines in the array. Cooling of the individual modules may be accomplished using a support member made from an enhanced heat transfer material or placing an enhanced heat transfer material layer between the modules. The devices on the module may be encapsulated, and the modules may be constructed in a chip first or cavity-down configuration. Methods are also disclosed.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: October 10, 2000
    Assignee: Raytheon E-Systems, Inc.
    Inventors: Alan J. Lauder, Simon G. Wood, Jr.
  • Patent number: 6128200
    Abstract: A butt-joint CPU mounting structure includes a connector having two opposite faces. Each face has a receiving slot disposed therein adapted to respectively and receivingly engage with a CPU module and an edge of a main board of a computer thereby connecting the CPU module to the main board. The receiving slots are arranged in alignment with each other whereby the CPU module is substantially coplanar with the main board. A CPU holder includes two support members each defining a channel for receiving opposite side flanges of the connector. Bolts are used to secure the support members to the side flanges of the connector. The CPU module is received between the two support members whereby opposite edges of the CPU module are engaged and supported by the support members. A connection member is connected between the two support members for strengthening the mechanical structure thereof. The support members are provided with bolt holes through which bolts extend for engaging with a housing of the computer.
    Type: Grant
    Filed: February 18, 1999
    Date of Patent: October 3, 2000
    Inventor: Ho-Kang Chu
  • Patent number: 6128199
    Abstract: A resistance element, a capacitor and an intermediate electrode are formed on a substrate. The capacitor and the resistance element are connected with the intermediate electrode interposed. Two terminal electrode portions are connected to each other through the intermediate electrode.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: October 3, 2000
    Assignee: Rohm Co., Ltd.
    Inventor: Shigeru Kambara
  • Patent number: 6125042
    Abstract: The present invention is directed to an integrated circuit package having improved EMI characteristics. In accordance with one aspect of the invention, a ball grid array integrated circuit package is provided for attachment to a circuit board. The circuit package includes a substrate having a semiconductor die defining an electronic circuit formed thereon. A matrix of spherically-shaped package leads is disposed adjacent the substrate and opposite the semiconductor die. Conductive elements, such as bond wires, electrically connect circuit points on the semiconductor die to the package leads. Further, at least one conductive element electrically interconnects each of the leads that define a perimeter of the matrix of package leads, for electrical connection to ground. In the preferred embodiment, adjacent leads of the perimeter matrix are separated by a spacing that is no greater than 1/20 of the wavelength of the highest frequency electrical signal carried on any of the signal leads.
    Type: Grant
    Filed: April 10, 1998
    Date of Patent: September 26, 2000
    Assignee: Lucent Technologies, Inc.
    Inventors: Fred W. Verdi, Richard Haynes
  • Patent number: 6118665
    Abstract: A flexible printed circuit having wiring patterns printed on a flexible resin film, comprising a narrow flexible area having first wiring patterns and constituting a flexible wiring part and a broad connection area adapted to be adhered to a main board and having second wiring patterns connected to the first wiring patterns and adapted to be electrically connected to wiring patterns on the main board. The second wiring patterns serve to electrically connect the first wiring patterns of the flexible wiring part to the wiring patterns on the main board. Also included is a conductive adhesion surface formed on the broad connection area along a side of the main board, having a width larger than a width of the first wiring patterns, and extending from an inside of a region to an outside thereof. The region is defined in the broad connection area by extending a boundary of the flexible area into the broad connection area.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: September 12, 2000
    Assignee: Fujitsu Limited
    Inventors: Katsuhiko Kishida, Katsunori Tanaka, Toshiya Onodera, Hirofumi Miyamoto
  • Patent number: 6118671
    Abstract: Ceramic circuit substrate which is sintered at 900 to 1,050.degree. C. and have low relative dielectric constant, thermal expansion coefficient comparable to that of silicon, and high bending strength, and a method of manufacturing are provided by using a glass with a softening point of 850 to 1,100.degree. C., that is, a glass having a composition included in an area in FIG. 1 (triangular composition diagram of SiO.sub.2 --B.sub.2 O.sub.3 --R.sub.2 O, a composition is represented by the position of a small circle, the number in a small circle represents the composition number) defined with lines connecting points representing the first, third, tenth, eleventh, and fourth compositions respectively as raw material.
    Type: Grant
    Filed: June 24, 1998
    Date of Patent: September 12, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Hirayoshi Tanei, Shoichi Iwanaga, Masahide Okamoto, Masato Nakamura, Kousaku Morita, Shousaku Ishihara, Fumikazu Tagami, Norio Sengoku, Tsuyoshi Fujita, Fumiyuki Kobayashi
  • Patent number: 6118664
    Abstract: A plug-in surge protector having an improved handle for facilitating and isolating the removal of an individual protector from a protector panel without interfering with adjacent protectors. The plug-in protector comprises a body having a front end and a rear end. Extending from the rear end of the body are terminals for plugging into sockets on a protector panel. Extending from the front end of the body is a handle having a reduced width and concave upper and lower surfaces. On the concave surfaces are horizontal teeth running across the width of the handle. It is preferable that the teeth are tilted towards the rear end of the body and against the direction of removal of the protector from the panel. The reduced width of the handle allows the removal of a single protector without touching or interfering with adjacent protectors plugged into the panel. The teeth on the handle increases the frictional surface area to facilitate removal of the protector from the panel.
    Type: Grant
    Filed: January 13, 1999
    Date of Patent: September 12, 2000
    Assignee: Lucent Technologies, Inc.
    Inventor: Bassel Hage Daoud
  • Patent number: 6115264
    Abstract: A multilayer high frequency electronic component having a greatly reduced resistance component of a signal line which functions as an inductor is constructed such that the signal line includes at least two conductor patterns provided on the surface of insulation sheets. The at least two conductor patterns have substantially the same shape and different pattern widths. The at least two conductor patterns are arranged to extend continuously across an insulation layer.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: September 5, 2000
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Koji Nosaka
  • Patent number: 6115261
    Abstract: A sensor mount for mounting a sensor to a substrate having a support member, a substrate attachment surface, and a sensor attachment surface. The support member can be attached to the substrate at the substrate attachment surface and the sensor can be attached to the support member at the sensor attachment surface. The sensor mount is shaped so an oblique angle is formed between the plane that includes the substrate attachment surface and the plane that includes the sensor attachment surfaces. Preferably, the support member has a wedge shape.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: September 5, 2000
    Assignee: Honeywell Inc.
    Inventors: William P. Platt, Dale J. Hagenson, Douglas P. Mortenson
  • Patent number: 6115260
    Abstract: A terminal structure in a memory module includes a male connector having a plurality of terminal strips adapted to be engaged with the terminal tongues in the female socket. Each of the terminal strips has an obstacle removal portion defined therein for removing foreign matter present on at least one of the terminal tongues.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: September 5, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takao Nakajima, Tetsurou Tsuji, Tetsuro Washida
  • Patent number: 6111756
    Abstract: A universal multi-chip interconnect system using a set of at least two types of standardized interconnect components is disclosed. One of the component types comprises a chip carrier capable of holding at least one IC chip in a first portion thereof and providing a plurality of standardized interconnections from the first portion to one or more second portions of the carrier, where one or more interconnect components of a different type may be connected. Another of the component types comprises a bridge connector which is capable of connecting to two or more chip carriers at their second portions. Each bridge connector has at least two interconnect portions which are capable of connecting to chip carriers at their second portions, and a standardized pattern of interconnect wires between the interconnect portions.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: August 29, 2000
    Assignee: Fujitsu Limited
    Inventor: Larry L. Moresco