Abstract: The present invention provides a method of manufacturing a semiconductor device, which is capable of reducing variations in the rate of occurrence of failures at individual connecting portions in the semiconductor device. According to the semiconductor device manufacturing method, a Cu-containing TiN layer, which serves as a cap layer (130 (310)), is formed using a Cu-containing Ti target. Cu contained in the Cu-containing TiN layer is diffused into an Al—Cu wiring (120 (320)) located in a portion electrically connected to an interlayer wiring (200) by heat treatment.

Abstract: In a method for fabricating a silicon-on-insulation wafer having fully processed devices in its upper-most silicon layer, the wafer is reduced in thickness from a surface opposite to the device layer surface by performing a first etching step of etching the semiconductor substrate to the insulation layer, so that the insulation layer functions as an etch stop layer, and a second etching step of etching the insulation layer to the semiconductor device layer, so that the semiconductor device layer functions as an etch stop layer. The semiconductor device layer is then separated into individual chips for fabricating a three-dimensionally integrated circuit thereof.

Abstract: The present invention provides semiconductor devices having at least one silicon region in a silicon carbide wafer in which is fabricated a low voltage semiconductor device such as for example, MOSFET devices, BiCMOS devices, Bipolar devices, etc., and on the same chip, at least one silicon carbide region in which is fabricated a high voltage (i.e., >1000V) semiconductor device using techniques well known in the art, such as for example, LDMOSFET, UMOSFET, DMOSFET, IGBT, MESFET, and JFET devices.

Abstract: A structure and a method for forming cells in power line areas between macro cell in a macro block area. In a power line level, a pin is formed between VSS and VDD lines. The pin is connected to the buffer cell. Next a signal line layer is formed and the signal line is connected to the pin and to a driver. In a first embodiment the driver is formed in a standard cell area. In a second embodiment the driver is formed in a micro cell. A signal line is connected to the pin and the driver.

Abstract: A new process is provided for the creation of sub-micron conductive lines and patterns. A conductive layer is deposited over the surface of a substrate, a sacrificial layer that differs with the conductive layer in etch characteristics is deposited over the surface of the conductive layer. The sacrificial layer is patterned and etched, creating an opening in the sacrificial layer that aligns with but is larger in cross section than the to be created sub-micron conductive lines and patterns. A spacer layer is deposited over the surface of which a hard mask layer is deposited, filling the opening in the sacrificial layer. The hard mask layer is polished down to the surface of the spacer layer, leaving the hard mask layer in place overlying the spacer layer inside the opening created in the sacrificial layer.

Abstract: The present invention is directed to a method of performing alignment during processing of a semiconductor device. The method is comprised of: performing alignment registration on a plurality of layers on said semiconductor device; measuring misregistration of said alignment registration in relation to a predetermined standard alignment key; and generating an offset for a subsequent process layer on said semiconductor using said measure misregistration.