Abstract: A method for determining a combination of shift operations whose results, when added, or added and subtracted in combination, give any desired accuracy for integer division by a known integer divisor.

Abstract: A rounding means is associated with a carry propagate adder of a floating point processor in order to reduce latency and enhance performance. The rounding mechanism performs a rounding function approximately simultaneously with an addition function performed by the carry propagate adder on fraction inputs FA, FB to ultimately derive a resultant fraction FR, thereby eliminating the need for a conventional post-normalize incrementer. The rounding mechanism has a carry select adder and rounding logic network. The rounding logic network communicates with the carry propagate adder and the carry select adder in order to provide rounding information to the carry select adder. The carry select adder and the rounding logic network jointly provide a rounded output, which is then normalized by the normalizer to thereby derive the resultant fraction.

Abstract: A pseudo-random sequence generator characterized by comprising a plurality of substantially similar elements adapted to operate in parallel, each said element including: means for entering at least first and second different numbers into that element, and means for processing said numbers including multiplier means for creating intermediate numbers of higher value than either of said first and second numbers and modulating means for subsequently reducing those intermediate numbers to values below the higher of said first and second numbers, whereby said processing means is adapted to generate a first sequence that has a period of not less than half the number range of said first sequence; and means for combining the first sequences, number by number, from all the parallel elements to permit generation of a pseudo-random sequence of higher period.

Abstract: This shift amount detector determines the shift amount to normalize binary bit data. It is provided with means to add, to an n bit data to be normalized, at least one bit of logical value "0" on the side of the least significant bit. The data with additional logical value "0" has its bits reversed by the bit reversing circuit when the data is negative or positive. The data with the additional logical value "0" is input to the bit detecting circuit as it is or as data with reversed bits according to the selection by the selecting circuit. The bit detecting circuit detects the bit position where "1" or "0" appears for the first time by searching the bits one by one starting from the most significant bit and outputs the result of detection to the shift amount calculating circuit. The shift amount calculating circuit determines the shift amount based on the detected bit position.

Abstract: A portable computer telephone device comprising a portable personal computer and a mobile phone integrated into one and the same body structure said body having a display screen (3) and a keyboard member (2) for operating the computer and the mobile telephone. To improve the convenience of use of such an integrated device, the keyboard member (2) is arranged to be movable between open and closed positions with respect to the rest of the body structure (1) in such a way that in the open position the whole display screen (3) and at least the whole keyboard (4, 5) of the computer are accessible for operating the computer and in the closed position the keyboard member (2) covers a part of the display screen and leaves the buttons (6) of the mobile telephone part 3(a) of the display screen accessible for operating the mobile telephone.

Abstract: The invention relates to a system for checking tool breakages on a machining center equipped with a numerically controlled machine tool (100) and a tool magazine (200), in which there are at least two cameras (401,402), processing and control means (600), the system thus making it possible to take photographs of tools intended to carry out the machining of a part in one or two planes, one photograph being taken prior to machining and the other afterwards, the photographs obtained then being compared in order to detect any abnormal conditions on the tools, the photographs taken by the second camera (402) being focussed on the basis of length information obtained with the photographs taken by the first camera.

Abstract: This device includes a control signal generator receiving as input a clock signal whose active front is synchronous with the bits of the mesh, and a reinitialization signal before each comparison, and whose group of outputs is connected to a parallel-series converter receiving as input the reference in parallel form from a programmable reference generator receiving as input an initial reference and a signal of variable level depending on the time, this reference generator being adapted to deliver a programmed reference depending on the desired bit maskings, the output of the parallel-series converter delivering a signal representative of the selected bit of the reference and being connected to the input of means of detection of transition of the output signal of the converter and of generation of a signal for inhibiting the current processing of a bit in response to the detection of a transition in this signal.

Abstract: In an arithmetic apparatus operands are represented as powers of a generator so that multiplications can be performed as simple additions. However this makes actual addition difficult. Additions are therefore performed by means of a subtractor circuit (1), a Zech table (2) and an adder circuit (3). In order to perform these additions when each power is in plural residue form (x.sub.1, x.sub.2 and y.sub.1, y.sub.2) and give the result power also in plural residue form (i.sub.1, i.sub.2), the subtractor circuit comprises subtractor subcircuits (1A, 1B), the adder circuit comprises adder subcircuits (3A, 3B) and the Zech table is arranged to produced its output also in plural residue form (j.sub.i, j.sub.2). In order to obtain the correct result even when the power representation y.sub.1, y.sub.2 represents an operand value of zero the apparatus also includes a detector (58) for this condition, this controlling a multiplexer (61) which then conducts the other operand (x.sub.1, y.sub.

Abstract: The circuit includes a cascaded array of digital circuit blocks that together implement a matrix multiplication in each channel of a color video signal processing system. Each circuit block includes two registers for multiplying or dividing two input digital signals by respective powers of two according to programmable bit shifts. The resultant signals are arithmetically combined according to a programmable arithmetic function to provide an output signal. By mask programming the arithmetic function and the bit lenghts of the shifts for each block and by cascading the programmed blocks, the multipler coefficients of the matrix are established and the output signal represents a specified color matrix operation.

Abstract: A word serial multiplier includes a first circuit loop for loading a parallel-bit multiplier, and in response to a clock signal sequentially produces a gate signal corresponding to a sequence of bits of the multiplier sample in descending order of significance. A second circuit loop loads a multiplicand sample and in response to the clock signal successively divides the multiplicand sample by the factor two. The more significant bits, exclusive of the least significant bit, of the divided multiplicand sample are coupled to a gating circuit. The gating circuit passes the more significant bits to the input of an accumulator if the corresponding bits of the gate signal exhibit a predetermined state. After a number of cycles of the clock signal, corresponding to the number of bits m of the multiplier sample, the accumulator produces a scaled product equal to the muliplicand times the multiplier times the scale factor of 2.sup.-(m-1).

Abstract: A data entry keypad assembly, comprising a keypad including an array of keys, and a positioning locator secured to the keypad to form a unitary keypad assembly therewith, whereby the keypad assembly is selectively positionable at a desired locus of a data field to permit accurate inputting of data by the keypad to a digital computer operatively coupled therewith. Data processing systems comprising a digital computer operatively connected to such keypad assembly are disclosed, together with a source code computer program operatively associable with a digital computer of a type employing an MS-DOS, or compatible, operating system, and arranged to actuate audio signal generating means, to provide audio feedback indicative of a specific key of the keypad being actuated, and to assist in minimizing data entry inputting errors.

Abstract: Provision is made in programmable alphanumeric calculator systems to provide functional controls from the keyboard for setting up various keyboard operational modes so that fewer keys on the keyboard are necessary. Thus, computer control commands are initiated in a control mode for entries of the commands in response for two successive keystrokes. In particular the entry of a full set of twenty six alphabetic characters typically with fewer than twelve keys is achieved by providing a different operating mode than for the entry of numeric digits from the keys with a single keystroke. Accordingly the alphabetic characters are entered with two successive keystrokes from a subset of six or more keys in different embodiments.

Abstract: A small hand-held electronic device that contains all of the normally interesting statistics for a baseball player or team. The user interface comprises a visual display and a keyboard having alphabet keys, an ENTER key, cursor keys for scrolling, and statistic keys for selecting the statistic of interesting. The system electronics includes a microprocessor and a large solid state non-volatile memory array containing the detailed statistical records of hundreds of baseball players. The user turns on the device and selects a player or team by entering two or three characters of the name via the alphabet keys. A series of choices are displayed on the screen and the user scrolls through the list using the cursor keys (up and down). When the desired player or team is displayed, the user presses the appropriate statistic key. The device displays the cumulative statistics; previous year statistics are displayed by the use of the cursor keys.

Abstract: A left justification scale factor generator is described which is capable of scaling numbers for binary number groups off one, two, three and four bit groups. Two basic building block circuits are utilized in the scale factor generator's priority encoder, which looks at four binary bits and produces a two bit binary count that corresponds to the first non-zero input found, and an algebraic priority encoder which also receives a reference signal that allows it to indicate the significance of the priority detection level. By sensing correction factors at the first level of the system, the number of logic levels are kept to a minimum.

Abstract: A method and apparatus are disclosed which provide for the removal of distortion present in a digital output signal from a linear analog signal processing system. Two applications are disclosed: digital compensation and digital equalization. Digital compensation provides for the removal of distortion from a single signal processing system. In particular, an adaptive digital filter operates to provide processing of an output signal from the signal processing system in accordance with correction criteria determined by a controller in response to a training signal. Digital equalization is employed with respect to a plurality of signal processing systems, and provides equalization of an output signal from one signal processing system in accordance with characteristics of a selected signal processing system.

Abstract: A modulo arithmetic unit for providing a sum or difference of two numbers of arbitrary value in a selected one of a plurality of moduli is provided. Each modulus has a lower and an upper boundary and a range of intermediate values. First and second adders are provided for respectively providing first and second outputs which respectively represent outputs compensated for and not compensated for a possible wraparound of the upper or lower boundary. Control circuitry is used to detect whether a wraparound occurred during the calculation depending upon the value of selective interstage carry signals of the first and second adders. The correct output is provided as a selected one of the outputs of the first and second adders in response to the control circuitry.

Abstract: A divider apparatus includes a divisor register for storing a divisor, a partial remainder register for storing a dividend or a partial remainder, a predictor for predicting a partial quotient, a multiplier for multiplying the content of the divisor register, and a first adder for subtracting the output of the multiplier from the content of the partial remainder register and for calculating the partial remainder.

Abstract: When a positive or a negative overflow error condition is encountered, the present invention substitutes the most positive or most negative value for the erroneous sample. The sign bit of a potentially erroneous value is inverted to form the MSB of the substitute value, and this value is, in turn, inverted and expanded to form the n-l LSB's of the substitute value. If an overflow error condition is detected, the erroneous value is replaced by the substitute value.