Abstract: The invention provides a display panel, a transparent member placed on at least one of an incident surface and an emergent surface of the display panel, and a gap member placed between at least one of the display panel and the transparent member to form a gap therebetween. Accordingly, the effect of cooling the liquid crystal panel, the transparent member, and a display panel case is enhanced to extend the lifetime of the device and to reduce noise.

Abstract: A magnetic memory cell and method of manufacturing thereof, wherein the angle between the shape anisotropy axis and the intrinsic anisotropy axis of the magnetic material layer is optimized to minimize fluctuations in the switching field. The angle between shape anisotropy axis and intrinsic anisotropy axis is preferably between 45 and less than 90 degrees. Magnetic layers may be used having increased thickness, resulting in increased activation energy. Magnetic memory cells may be manufactured that are more stable for long term storage and have improved write margins.

Abstract: In copper plating using a damascene method, in order to prevent cost rise, dishing, erosion and the like due to the protrusion of plating on the dense wiring area to increase the time for CMP polishing, the copper plating is performed so that the current step of the copper plating has only one step for flowing current in the direction opposite to the direction of growing the plating as shown in FIG. 1. In this time, this opposite direction current step is performed under the condition of a current-time product within a range between 1.0 and 120 mA×sec/cm2.

Abstract: The power semiconductor device includes a plurality of trenches disposed in a surface of a semiconductor active layer to reach a first base layer of a first conductivity type. The trenches are disposed at intervals to partition a main cell and a dummy cell. In the main cell, a second base layer of a second conductivity type and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode and gate insulating film are disposed in each trench. A partition structure is disposed in the surface of the semiconductor active layer to electrically isolate the buffer layer from the emitter electrode.

Abstract: A method of manufacturing a contact is disclosed. A substrate is provided, and a first dielectric layer and a metal layer are formed thereon in sequence. A second dielectric layer is formed on the metal layer and the first dielectric layer. A bottom contact is formed in the second dielectric layer to electrically connect to the metal layer. A node contact is formed in the first and second dielectric layers. A capacitor is formed on the dielectric layer to electrically connect to the node contact, and a middle contact is formed on the second dielectric layer to electrically connect to the bottom contact. A third dielectric layer is formed on the capacitor, the middle contact and the second dielectric layer. A top contact is formed in the third dielectric layer to electrically connect to the middle contact.

Abstract: Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or {fraction (1/16)}) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

Abstract: A method for passivating copper, aluminum, or other refractory metal films using ammonia-free silicon nitride and structures produced by the method. A thin film transistor for use in a liquid crystal display and a method of constructing the same, wherein the transistor has a gate, a source and a drain, and a gate insulator between the gate and an active silicon layer. The improvement is a layer of the ammonia-free silicon nitride deposited between the copper,aluminum, or other refractory metal gate and the gate insulator. Further,. the gate is copper, aluminum, or another refractory metal and is deposited directly on the substrate. The layer of ammonia-free silicon nitride is also deposited on portions of the substrate adjacent the gate and the gate line extending therefrom. The layer is made in a plasma-enhanced chemical vapor deposition process wherein the gas mixture comprises one part silane to 135 parts nitrogen to 100 parts helium and 100 parts hydrogen.

Abstract: Provided herein is a method of depositing a film on a substrate in a high temperature chemical vapor deposition (CVD) reactor, comprising the steps of polishing sharp corner(s) of the surface of a heater, wherein the heater provides heat to the substrate for deposition; coating the polished heater surface with a coating material; and depositing a film on the substrate in the CVD reactor, wherein the substrate is heated through the coated polished heater. Such method of polishing may also be used for reducing pitting of a coated heater and protecting the heater from corrosive environment in a CVD reactor.

Abstract: A fabrication method for a borderless buried bit line is described. A substrate wherein a plurality of word lines and source/drain regions formed thereon is provided. A first insulation material is formed over the substrate and a node landing pad is formed in the first insulation material, wherein the node landing pad is covered by a second insulation material. A bit line contact is further formed in the first insulation material, wherein the bit line contact is covered by a third insulation material. Therefore, a trench is further formed along the sides of the bit line contact, traversing across the first insulation material. A partial filling of the trench with a conductive material, followed by filling the trench with a fourth insulation layer to complete the formation of the buried bit line.

Abstract: A manufacturing method of an LED of a type of round concave cup with a flat bottom comprises two manufacturing steps. At first stage of concave cup printer circuit board, a printed circuit board is placed in a CNC computer driller, and a special miller cutting is used to drill a concave cup with a round flat bottom at the speed of 12000 to 25000 rps (the depth of the cup must be set). After drilling process is complete, a sand ejector serves to polish the interior of the concave cup. Then, plating with copper ions (which is similar to the penetrating process of guide holes in a general printed circuit board), after plating nickel step and plating metal step are completed, the first stage is finished. In the second stage, a manufacturing method of concave cup type LED is performed. The concave cup type LED in the first stage is processed through the steps of point gluing, fixing chip, baking, bonding, quality controlling, filling glue, and baking again. Then a multiple usage concave cup type LED is fabricated.

Abstract: A semiconductor synchronous dynamic random access memory device has an input/output masking function in a block write mode, plural bit line pairs are concurrently connected to a pair of data lines charged to a power voltage level by a precharge circuit in the input/output masking function so as to prevent memory cells from current flowing out from differential amplifiers, and the precharge circuit has not only p-channel type charging transistors but also n-channel enhancement type charging transistors; even if the bit line pairs are connected to the pair of data lines, the n-channel enhancement type charging transistors supplement the current through the data line pair to the bit line pairs, and prevent potential differences on the bit line pairs from undesirable destruction.

Abstract: A test circuit for observing charge retention characteristics of cells in a flash memory array is disclosed. Unlike prior art structures, the present circuit monitors both charge loss and charge gain of cells in the array. In this way, cells having conduction thresholds below a desired target threshold and cells having conduction thresholds above a desired target threshold can both be observed. The circuit includes a regular memory array, and a mirror array formed with devices having opposite channel types to the regular array. By identifying and evaluating more accurately the threshold characteristics of a particular cell design or cell process, improvements can be made to such designs and processes in a more rapid and optimal fashion.

Abstract: A composite mode substrate voltage generation circuit for a DRAM which has a memory cell block and a peripheral circuit block formed on a single substrate.